Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2019066993) WARPAGE MITIGATION STRUCTURES CREATED ON SUBSTRATE USING HIGH THROUGHPUT ADDITIVE MANUFACTURING
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2019/066993 International Application No.: PCT/US2017/054677
Publication Date: 04.04.2019 International Filing Date: 30.09.2017
IPC:
H01L 23/367 (2006.01) ,H01L 23/04 (2006.01) ,H01L 23/00 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
36
Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
367
Cooling facilitated by shape of device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
02
Containers; Seals
04
characterised by the shape
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
EID, Feras [LB/US]; US
Inventors:
EID, Feras; US
Agent:
ROJO, Estiven; US
BRASK, Justin K.; US
AUYEUNG, Al; US
BERNADICOU, Michael A.; US
BLAIR, Steven R.; US
BLANK, Eric S.; US
COFIELD, Michael A.; US
DANSKIN, Timothy A.; US
HALEVA, Aaron S.; US
MAKI, Nathan R.; US
MARLINK, Jeffrey S.; US
MOORE, Michael S.; US
PARKER, Wesley E.; US
PUGH, Joseph A.; US
RASKIN, Vladimir; US
STRAUSS, Ryan N.; US
WANG, Yuke; US
YATES, Steven D.; US
SULLIVAN, Stephen G.; US
Priority Data:
Title (EN) WARPAGE MITIGATION STRUCTURES CREATED ON SUBSTRATE USING HIGH THROUGHPUT ADDITIVE MANUFACTURING
(FR) STRUCTURES D'ATTÉNUATION DE GAUCHISSEMENT CRÉÉES SUR UN SUBSTRAT À L'AIDE D'UNE FABRICATION ADDITIVE À HAUT RENDEMENT
Abstract:
(EN) Device package and method of forming a device package are described. The device package has a substrate with dies disposed on the substrate. Each die has a bottom surface that is electrically coupled to the substrate and a top surface. The device package further includes a plurality of stiffeners disposed directly on the substrate. The stiffeners may be directly attached to a top surface of the substrate without an adhesive layer. The device package may include stiffeners with one or more different sizes and shapes, including at least one of a rectangular stiffener, a picture frame stiffener, a L-shaped stiffener, a H-shaped stiffener, and a round pillar stiffener. The device package may have the stiffeners disposed on the top surface of the substrate using a cold spray process. The device package may also include a mold layer formed around and over the dies, the stiffeners, and the substrate.
(FR) L'invention concerne un boîtier de dispositif et un procédé de formation de boîtier de dispositif. Le boîtier de dispositif a un substrat avec des puces disposées sur le substrat. Chaque puce a une surface inférieure qui est électriquement couplée au substrat et une surface supérieure. Le boîtier de dispositif comprend en outre une pluralité de raidisseurs disposés directement sur le substrat. Les raidisseurs peuvent être directement fixés à une surface supérieure du substrat sans couche adhésive. Le boîtier de dispositif peut comprendre des raidisseurs ayant une ou plusieurs tailles et formes différentes, comprenant au moins un élément parmi un raidisseur rectangulaire, un raidisseur en forme de cadre d'image, un raidisseur en forme de L, un raidisseur en forme de H, et un raidisseur en forme de pilier rond. Le boîtier de dispositif peut comporter les raidisseurs disposés sur la surface supérieure du substrat à l'aide d'un procédé de pulvérisation à froid. Le boîtier de dispositif peut également comprendre une couche de moule formée autour et au-dessus des puces, des raidisseurs et du substrat.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)