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1. (WO2019066992) PACKAGE WITH A HIGHLY CONDUCTIVE LAYER DEPOSITED ON DIE USING THROUGHPUT ADDITIVE DEPOSITION PRIOR TO TIM1 DISPENSE
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Pub. No.: WO/2019/066992 International Application No.: PCT/US2017/054676
Publication Date: 04.04.2019 International Filing Date: 30.09.2017
IPC:
H01L 23/367 (2006.01) ,H01L 23/40 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
36
Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
367
Cooling facilitated by shape of device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
40
Mountings or securing means for detachable cooling or heating arrangements
Applicants:
EID, Feras [LB/US]; US
SWAN, Johanna M. [US/US]; US
CHAN ARGUEDAS, Sergio [CR/US]; US
BEATTY, John J. [US/US]; US
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
EID, Feras; US
SWAN, Johanna M.; US
CHAN ARGUEDAS, Sergio; US
BEATTY, John J.; US
Agent:
ROJO, Estiven; US
BRASK, Justin K.; US
AUYEUNG, Al; US
BERNADICOU, Michael A.; US
BLAIR, Steven R.; US
BLANK, Eric S.; US
COFIELD, Michael A.; US
DANSKIN, Timothy A.; US
HALEVA, Aaron S.; US
MAKI, Nathan R.; US
MARLINK, Jeffrey S.; US
MOORE, Michael S.; US
PARKER, Wesley E.; US
PUGH, Joseph A.; US
RASKIN, Vladimir; US
STRAUSS, Ryan N.; US
WANG, Yuke; US
YATES, Steven D.; US
SULLIVAN, Stephen G.; US
Priority Data:
Title (EN) PACKAGE WITH A HIGHLY CONDUCTIVE LAYER DEPOSITED ON DIE USING THROUGHPUT ADDITIVE DEPOSITION PRIOR TO TIM1 DISPENSE
(FR) BOÎTIER DOTÉ D'UNE COUCHE HAUTEMENT CONDUCTRICE DÉPOSÉE SUR UNE PUCE PAR DÉPÔT ADDITIF AVANT UNE APPLICATION DE TIM1
Abstract:
(EN) A device package and a method of forming a device package are described. The device package has dies disposed on a substrate, and one or more layers with a high thermal conductivity, referred to as the highly-conductive (HC) intermediate layers, disposed on the dies on the substrate. The device package further includes a lid with legs on an outer periphery of the lid, a top surface, and a bottom surface. The legs of the lid are attached to the substrate with a sealant. The bottom surface of the lid is disposed over the one or more HC intermediate layers and the one or more dies on the substrate. The device package may also include thermal interface materials (TIMs) disposed on the HC intermediate layers. The TIMs may be disposed between the bottom surface of the lid and one or more top surfaces of the HC intermediate layers.
(FR) L'invention concerne un boîtier de dispositif et un procédé de formation de boîtier de dispositif. Le boîtier de dispositif comprend des puces disposées sur un substrat, et une ou plusieurs couches de haute conductivité thermique, appelées couches intermédiaires hautement conductrices (HC), disposées sur les puces du substrat. Le boîtier de dispositif comprend en outre un couvercle doté de pattes situées sur une périphérie extérieure du couvercle, une surface supérieure et une surface inférieure. Les pattes du couvercle sont fixées au substrat au moyen d'un agent de scellement. La surface inférieure du couvercle est disposée sur la ou les couches intermédiaires HC et sur la ou les puces du substrat. Le boîtier de dispositif peut également comprendre des matériaux d'interface thermique (TIM) disposés sur les couches intermédiaires HC. Les TIM peuvent être disposés entre la surface inférieure du couvercle et une ou plusieurs surfaces supérieures des couches intermédiaires HC.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)