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1. (WO2019066991) PCB EMBEDDED STACK FOR IMPROVED ELECTRICAL FUNCTIONALITY AND TEST
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Pub. No.: WO/2019/066991 International Application No.: PCT/US2017/054675
Publication Date: 04.04.2019 International Filing Date: 30.09.2017
IPC:
H01L 25/065 (2006.01) ,H01L 25/07 (2006.01) ,H01L 23/52 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
Applicants:
ELSHERBINI, Adel A. [EG/US]; US
LIFF, Shawna M. [US/US]; US
FALCON, Javier A. [US/US]; US
SWAN, Johanna M. [US/US]; US
SAUCEDO, Joe R. [US/US]; US
MYERS, Preston T. [US/US]; US
LOPEZ, Albert S. [US/US]; US
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
ELSHERBINI, Adel A.; US
LIFF, Shawna M.; US
FALCON, Javier A.; US
SWAN, Johanna M.; US
SAUCEDO, Joe R.; US
MYERS, Preston T.; US
LOPEZ, Albert S.; US
Agent:
ROJO, Estiven; US
BRASK, Justin K.; US
AUYEUNG, Al; US
BERNADICOU, Michael A.; US
BLAIR, Steven R.; US
BLANK, Eric S.; US
COFIELD, Michael A.; US
DANSKIN, Timothy A.; US
HALEVA, Aaron S.; US
MAKI, Nathan R.; US
MARLINK, Jeffrey S.; US
MOORE, Michael S.; US
PARKER, Wesley E.; US
PUGH, Joseph A.; US
RASKIN, Vladimir; US
STRAUSS, Ryan N.; US
WANG, Yuke; US
YATES, Steven D.; US
SULLIVAN, Stephen G.; US
Priority Data:
Title (EN) PCB EMBEDDED STACK FOR IMPROVED ELECTRICAL FUNCTIONALITY AND TEST
(FR) EMPILEMENT INTÉGRÉ DE CARTE DE CIRCUIT IMPRIMÉ POUR UNE FONCTIONNALITÉ ET UN TEST ÉLECTRIQUES AMÉLIORÉS
Abstract:
(EN) Embodiments include device packages and methods of forming the device packages. A device package may have a plurality of dies that are stacked. Each die may have one or more die contacts that are each electrically coupled to at least one die contact of another die with interconnects. For one embodiment, a substrate is disposed adjacent to the dies and has a first set and second set of pads. An encapsulation layer may be deposited over and around the dies, the interconnects, and the substrate. For one embodiment, the second set of pads on the bottom surface of the substrate are exposed. Additionally, the device package may include at least one interconnect having a first and second end, where the first end is connected to one die contact and the second end extends through the encapsulation layer to at least one pad of the first set of pads.
(FR) Des modes de réalisation de la présente invention comprennent des boîtiers de dispositif et des procédés de formation des boîtiers de dispositif. Un boîtier de dispositif peut avoir une pluralité de puces empilées. Chaque puce peut avoir un ou plusieurs contacts de puce qui sont chacun couplés électriquement à au moins un contact de puce d'une autre puce avec des interconnexions. Dans un mode de réalisation, un substrat est disposé adjacent aux puces et comporte un premier ensemble et un second ensemble de tampons. Une couche d'encapsulation peut être déposée sur et autour des puces, des interconnexions et du substrat. Dans un mode de réalisation, le second ensemble de tampons sur la surface inférieure du substrat sont exposés. De plus, le boîtier de dispositif peut comprendre au moins une interconnexion ayant une première et une seconde extrémité, la première extrémité étant reliée à un contact de puce et la seconde extrémité s'étendant à travers la couche d'encapsulation jusqu'à au moins un tampon du premier ensemble de tampons.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)