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1. (WO2019066989) SUBSTRATE INTEGRATED POSTS AND HEAT SPREADER CUSTOMIZATION FOR ENHANCED PACKAGE THERMOMECHANICS
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Pub. No.: WO/2019/066989 International Application No.: PCT/US2017/054673
Publication Date: 04.04.2019 International Filing Date: 30.09.2017
IPC:
H01L 23/367 (2006.01) ,H01L 23/12 (2006.01) ,H01L 23/40 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
36
Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
367
Cooling facilitated by shape of device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
40
Mountings or securing means for detachable cooling or heating arrangements
Applicants:
EDI, Feras [LB/US]; US
PADMANABHAN RAMALEKSHMI THANU, Dinesh [IN/US]; US
CHAN ARGUEDAS, Sergio A. [CR/US]; US
SWAN, Johanna M. [US/US]; US
BEATTY, John J. [US/US]; US
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
EDI, Feras; US
PADMANABHAN RAMALEKSHMI THANU, Dinesh; US
CHAN ARGUEDAS, Sergio A.; US
SWAN, Johanna M.; US
BEATTY, John J.; US
Agent:
ROJO, Estiven; US
BRASK, Justin K.; US
AUYEUNG, Al; US
BERNADICOU, Michael A.; US
BLAIR, Steven R.; US
BLANK, Eric S.; US
COFIELD, Michael A.; US
DANSKIN, Timothy A.; US
HALEVA, Aaron S.; US
MAKI, Nathan R.; US
MARLINK, Jeffrey S.; US
MOORE, Michael S.; US
PARKER, Wesley E.; US
PUGH, Joseph A.; US
RASKIN, Vladimir; US
STRAUSS, Ryan N.; US
WANG, Yuke; US
YATES, Steven D.; US
SULLIVAN, Stephen G.; US
Priority Data:
Title (EN) SUBSTRATE INTEGRATED POSTS AND HEAT SPREADER CUSTOMIZATION FOR ENHANCED PACKAGE THERMOMECHANICS
(FR) MONTANTS INTÉGRÉS DE SUBSTRAT ET PERSONNALISATION DE DIFFUSEUR DE CHALEUR POUR THERMOMÉCANIQUE D'EMBALLAGE AMÉLIORÉE
Abstract:
(EN) A device package and a method of forming a device package are described. The device package includes a plurality of posts disposed on a substrate. Each post has a top surface and a bottom surface that is opposite from the top surface. The device package also has one or more dies disposed on the substrate. The dies are adjacent to the plurality of posts on the substrate. The device package further includes a lid disposed above the plurality of posts and the one or more dies on the substrate. The lid has a top surface and a bottom surface that is opposite from the top surface. Lastly, an adhesive layer attaches the top surfaces of the plurality of posts and the bottom surface of the lid. The device package may also include one or more thermal interface materials (TIMs) disposed on the dies.
(FR) L'invention concerne un boîtier de dispositif et un procédé de formation de boîtier de dispositif. Le boîtier de dispositif comprend une pluralité de montants disposés sur un substrat. Chaque montant a une surface supérieure et une surface inférieure qui est opposée à la surface supérieure. Le boîtier de dispositif comprend également une ou plusieurs puces disposées sur le substrat. Les puces sont adjacentes à la pluralité de montants sur le substrat. Le boîtier de dispositif comprend en outre un couvercle disposé au-dessus de la pluralité de montants et de la ou des puces sur le substrat. Le couvercle comprend une surface supérieure et une surface inférieure qui fait face à la surface supérieure. Enfin, une couche adhésive fixe les surfaces supérieures de la pluralité de montants et la surface inférieure du couvercle. Le boîtier de dispositif peut également comprendre un ou plusieurs matériaux d'interface thermique (TIMs) disposés sur les puces.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)