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1. (WO2019066988) PCB/PACKAGE EMBEDDED STACK FOR DOUBLE SIDED INTERCONNECT
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Pub. No.: WO/2019/066988 International Application No.: PCT/US2017/054672
Publication Date: 04.04.2019 International Filing Date: 30.09.2017
IPC:
H01L 25/065 (2006.01) ,H01L 23/48 (2006.01) ,H01L 23/12 (2006.01) ,H01L 23/00 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
Applicants:
LIFF, Shawna M. [US/US]; US
ELSHERBINI, Adel A. [EG/US]; US
FALCON, Javier A. [US/US]; US
MYERS, Preston T. [US/US]; US
SAUCEDO, Joe R. [US/US]; US
LOPEZ, Albert S. [US/US]; US
SWAN, Johanna M.; US
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
LIFF, Shawna M.; US
ELSHERBINI, Adel A.; US
FALCON, Javier A.; US
MYERS, Preston T.; US
SAUCEDO, Joe R.; US
LOPEZ, Albert S.; US
SWAN, Johanna M.; US
Agent:
ROJO, Estiven; US
BRASK, Justin K.; US
AUYEUNG, Al; US
BERNADICOU, Michael A.; US
BLAIR, Steven R.; US
BLANK, Eric S.; US
COFIELD, Michael A.; US
DANSKIN, Timothy A.; US
HALEVA, Aaron S.; US
MAKI, Nathan R.; US
MARLINK, Jeffrey S.; US
MOORE, Michael S.; US
PARKER, Wesley E.; US
PUGH, Joseph A.; US
RASKIN, Vladimir; US
STRAUSS, Ryan N.; US
WANG, Yuke; US
YATES, Steven D.; US
SULLIVAN, Stephen G.; US
Priority Data:
Title (EN) PCB/PACKAGE EMBEDDED STACK FOR DOUBLE SIDED INTERCONNECT
(FR) EMPILEMENT INTÉGRÉ DE PCB/BOÎTIER POUR INTERCONNEXION DOUBLE FACE
Abstract:
(EN) Embodiments of a device package and a method of forming the device package are described. The device package has a substrate having a cavity and pads on at least one of a top and bottom surface, and a first die embedded in the cavity of the substrate. The device package includes a second die having an adhesive layer on a bottom surface of the second die, where the second die and the adhesive layer are disposed on the first die and substrate. The device package includes dies disposed on the second die and on top of one another to form a stack, wherein each die has die contacts on at least one of a top and bottom surface, where at least one of the die contacts of each die is electrically coupled to at least one of the die contacts of another die and pads of the substrate with interconnects.
(FR) Des modes de réalisation de l’invention concernent un boîtier de dispositif et un procédé de formation du boîtier de dispositif. Le boîtier de dispositif comprend un substrat ayant une cavité et des pastilles sur au moins l'une parmi une surface supérieure et une surface inférieure, et une première puce incorporée dans la cavité du substrat. Le boîtier de dispositif comprend une deuxième puce ayant une couche adhésive sur une surface inférieure de la deuxième puce, la deuxième puce et la couche adhésive étant disposées sur la première puce et le substrat. Le boîtier de dispositif comprend des puces disposées sur la deuxième puce et les unes sur les autres pour former un empilement, chaque puce comprenant des contacts de puce sur au moins l'une parmi une surface supérieure et une surface inférieure, au moins l'un des contacts de puce de chaque puce étant relié électriquement à au moins l'un des contacts de puce d'une autre puce et des pastilles du substrat avec des interconnexions.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)