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1. (WO2019066987) DIMENSION TOLERANT MULTI-MATERIAL STACK
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Pub. No.: WO/2019/066987 International Application No.: PCT/US2017/054671
Publication Date: 04.04.2019 International Filing Date: 30.09.2017
IPC:
H01L 25/065 (2006.01) ,H01L 25/07 (2006.01) ,H01L 23/495 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
495
Lead-frames
Applicants:
FALCON, Javier A. [US/US]; US
LIFF, Shawna M. [US/US]; US
MYERS, Preston T. [US/US]; US
LOPEZ, Albert S. [US/US]; US
SAUCEDO, Joe R. [US/US]; US
ELSHERBINI, Adel A. [EG/US]; US
SWAN, Johanna M. [US/US]; US
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
FALCON, Javier A.; US
LIFF, Shawna M.; US
MYERS, Preston T.; US
LOPEZ, Albert S.; US
SAUCEDO, Joe R.; US
ELSHERBINI, Adel A.; US
SWAN, Johanna M.; US
Agent:
ROJO, Estiven; US
BRASK, Justin K.; US
AUYEUNG, Al; US
BERNADICOU, Michael A.; US
BLAIR, Steven R.; US
BLANK, Eric S.; US
COFIELD, Michael A.; US
DANSKIN, Timothy A.; US
HALEVA, Aaron S.; US
MAKI, Nathan R.; US
MARLINK, Jeffrey S.; US
MOORE, Michael S.; US
PARKER, Wesley E.; US
PUGH, Joseph A.; US
RASKIN, Vladimir; US
STRAUSS, Ryan N.; US
WANG, Yuke; US
YATES, Steven D.; US
SULLIVAN, Stephen G.; US
Priority Data:
Title (EN) DIMENSION TOLERANT MULTI-MATERIAL STACK
(FR) EMPILEMENT DE MATÉRIAUX MULTIPLES À TOLÉRANCE DE DIMENSIONS
Abstract:
(EN) A method of forming a package layer includes disposing dies in a cavity of a dam formed on the adhesive layer, forming a first encapsulation layer around the dies in the cavity of the dam, wherein the first encapsulation layer is formed below the top surfaces of first dies, and disposing second dies on the top surfaces of the first dies. The method further includes forming a second encapsulation layer around the second dies, the interconnects, and on a top surface of the first encapsulation layer in the cavity, wherein the second encapsulation layer is formed below the top surfaces of the topmost dies of the second dies, disposes third dies on the top surfaces of the topmost dies of the second dies, and forming a third encapsulation layer over and around the third dies, the remaining interconnects, and a top surface of the second encapsulation layer in the cavity.
(FR) L'invention concerne un procédé de formation d'une couche de boîtier consistant à disposer des matrices dans une cavité d'un barrage formé sur la couche adhésive, à former une première couche d'encapsulation autour des matrices dans la cavité du barrage, la première couche d'encapsulation étant formée sous les surfaces supérieures des premières matrices, et à disposer des deuxièmes matrices sur les surfaces supérieures des premières matrices. Le procédé consiste en outre à former une deuxième couche d'encapsulation autour des deuxièmes matrices, les interconnexions, et sur une surface supérieure de la première couche d'encapsulation dans la cavité, la deuxième couche d'encapsulation étant formée sous les surfaces supérieures des matrices situées le plus en haut parmi les deuxièmes matrices, à disposer des troisièmes matrices sur les surfaces supérieures des matrices situées le plus en haut des deuxièmes matrices, et à former une troisième couche d'encapsulation sur les troisièmes matrices, sur les interconnexions restantes, et sur une surface supérieure de la deuxième couche d'encapsulation, et autour de ceux-ci, dans la cavité.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)