Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2019066976) MULTI-LEVEL DISTRIBUTED CLAMPS
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2019/066976 International Application No.: PCT/US2017/054634
Publication Date: 04.04.2019 International Filing Date: 29.09.2017
IPC:
H01L 25/16 (2006.01) ,H01L 23/498 (2006.01) ,H01L 23/522 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
16
the devices being of types provided for in two or more different main groups of groups H01L27/-H01L51/139
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
498
Leads on insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Blvd. Santa Clara, California 95054, US
Inventors:
CHOI, Beomseok; US
RADHAKRISHNAN, Kaladhar; US
LAMBERT, William; US
HILL, Michael; US
BHARATH, Krishna; US
Agent:
GUGLIELMI, David L.; US
Priority Data:
Title (EN) MULTI-LEVEL DISTRIBUTED CLAMPS
(FR) PINCES DISTRIBUÉES MULTINIVEAUX
Abstract:
(EN) An apparatus is provided which comprises: a first set of one or more contacts on a first die surface, the first set of one or more contacts to couple with contacts of an integrated circuit die, one or more multi-level voltage clamps coupled with the first set of one or more contacts, the one or more multi-level voltage clamps switchable between two or more voltages, one or more integrated voltage regulators coupled with the one or more multi-level voltage clamps, the one or more integrated voltage regulators to provide an output voltage, one or more through silicon vias (TSVs) coupled with the one or more integrated voltage regulators, and a second set of one or more contacts on a second die surface, opposite the first die surface, the second set of one or more contacts coupled with the one or more TSVs, and the second set of one or more contacts to couple with contacts of a package substrate. Other embodiments are also disclosed and claimed.
(FR) L'invention concerne un appareil qui comprend : un premier ensemble d'un ou plusieurs contacts sur une première surface de puce, le premier ensemble d'un ou plusieurs contacts à coupler avec des contacts d'une puce de circuit intégré, une ou plusieurs pinces à tension multiniveaux couplées au premier ensemble d'un ou plusieurs contacts, l'une ou plusieurs pinces à tension multiniveaux pouvant être commutées entre deux ou plusieurs tensions, un ou plusieurs régulateurs de tension intégrés couplés à l'une ou plusieurs pinces à tension multiniveaux, l'un ou plusieurs régulateurs de tension intégrés pour fournir une tension de sortie, un ou plusieurs trous d'interconnexion traversant le silicium (TSV) couplés à l'un ou plusieurs régulateurs de tension intégrés, et un second ensemble d'un ou plusieurs contacts sur une seconde surface de puce, opposée à la première surface de puce, le second ensemble d'un ou plusieurs contacts étant couplé à l'un ou plusieurs TSV, et le second ensemble d'un ou plusieurs contacts à coupler avec des contacts d'un substrat de boîtier. L'invention se rapporte également à d'autres modes de réalisation.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)