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1. (WO2019066971) DEVICE, METHOD AND SYSTEM FOR IMPOSING TRANSISTOR CHANNEL STRESS WITH AN INSULATION STRUCTURE
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Pub. No.: WO/2019/066971 International Application No.: PCT/US2017/054626
Publication Date: 04.04.2019 International Filing Date: 29.09.2017
IPC:
H01L 29/78 (2006.01) ,H01L 29/66 (2006.01) ,H01L 21/8238 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8238
Complementary field-effect transistors, e.g. CMOS
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Blvd. Santa Clara, CA 95054, US
Inventors:
MEHANDRU, Rishabh; US
Agent:
MILLER, Dermot G.; US
Priority Data:
Title (EN) DEVICE, METHOD AND SYSTEM FOR IMPOSING TRANSISTOR CHANNEL STRESS WITH AN INSULATION STRUCTURE
(FR) DISPOSITIF, PROCÉDÉ ET SYSTÈME PERMETTANT D'APPLIQUER UNE CONTRAINTE DE CANAL DE TRANSISTOR AU MOYEN D'UNE STRUCTURE D'ISOLATION
Abstract:
(EN) Techniques and mechanisms for imposing stress on transistors using an insulator. In an embodiment, an integrated circuit device includes a fin structure on a semiconductor substrate, wherein respective structures of two transistors are variously in or on the fin structure. A recess of the IC device, located in a region between the two transistors, extends at least partially through the fin structure. An insulator in the recess imposes stresses on respective channel regions of the two transistors. In another embodiment, compressive stresses or tensile stresses are imposed on the transistors with both the insulator and a buffer layer under the fin structure.
(FR) L'invention concerne des techniques et des mécanismes permettant d'appliquer une contrainte sur des transistors au moyen d'un isolateur. Dans un mode de réalisation, un dispositif à circuit intégré comprend une structure d'ailette sur un substrat semi-conducteur, des structures respectives de deux transistors se trouvant diversement dans la structure d'ailette ou sur cette dernière. Une partie évidée du dispositif à circuit intégré, située dans une région entre les deux transistors, se prolonge au moins partiellement dans la structure d'ailette. Un isolateur dans la partie évidée applique des contraintes sur des régions de canal respectives des deux transistors. Dans un autre mode de réalisation, des contraintes de compression ou des contraintes de traction sont appliquées sur les transistors au moyen de l'isolateur et d'une couche tampon sous la structure d'ailette.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)