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1. (WO2019066969) DEVICE, SYSTEM AND METHOD FOR PROVIDING INDUCTOR STRUCTURES
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Pub. No.: WO/2019/066969 International Application No.: PCT/US2017/054619
Publication Date: 04.04.2019 International Filing Date: 29.09.2017
IPC:
H01L 25/16 (2006.01) ,H01L 25/07 (2006.01) ,H01L 23/528 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
16
the devices being of types provided for in two or more different main groups of groups H01L27/-H01L51/139
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
528
Layout of the interconnection structure
Applicants:
GOMES, Wilfred [IN/US]; US
BOHR, Mark [US/US]; US
INGERLY, Doug [US/US]; US
KUMAR, Rajesh [IN/US]; US
KRISHNAMURTHY, Harish [IN/US]; US
DESAI, Nachiket Venkappayya [IN/US]; US
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard SANTA CLARA, California 95054, US
Inventors:
GOMES, Wilfred; US
BOHR, Mark; US
INGERLY, Doug; US
KUMAR, Rajesh; US
KRISHNAMURTHY, Harish; US
DESAI, Nachiket Venkappayya; US
Agent:
CONINGSBY, Donna Jo; US
MALLIE, Michael J.; US
VINCENT, Lester J.; US
Priority Data:
Title (EN) DEVICE, SYSTEM AND METHOD FOR PROVIDING INDUCTOR STRUCTURES
(FR) DISPOSITIF, SYSTÈME ET PROCÉDÉ DE FOURNITURE DE STRUCTURES D'INDUCTEUR
Abstract:
(EN) Techniques and mechanisms for providing an inductor with an integrated circuit (IC) die. In an embodiment, the IC die comprises integrated circuitry and one or more first metallization layers. The IC die is configured to couple to a circuit device including one or more second metallization layers, where such coupling results in the formation of an inductor which is coupled to the integrated circuitry. One or more loop structures of the inductor each span both some or all of the one or more first metallization layers and some or all of the one or more second metallization layers. In another embodiment, the IC die or the circuit device includes a ferromagnetic material to concentrate a magnetic flux which is provided with the inductor.
(FR) La présente invention concerne des techniques et des mécanismes destinés à fournir un inducteur dans une puce de circuit intégré (CI). Dans un mode de réalisation, la puce de CI comprend un circuit intégré et une ou plusieurs première(s) couche(s) de métallisation. La puce de CI est configurée pour se coupler à un dispositif de circuit comprenant une ou plusieurs seconde(s) couche(s) de métallisation, un tel couplage conduisant à la formation d'un inducteur qui est couplé au circuit intégré. Une ou plusieurs structure(s) en boucle de l'inducteur couvre(nt) chacune à la fois une partie ou la totalité desdites premières couches de métallisation et une partie ou la totalité desdites secondes couches de métallisation. Dans un autre mode de réalisation, la puce de CI ou le dispositif de circuit comprend/comprennent un matériau ferromagnétique permettant de concentrer un flux magnétique qui est prévu avec l'inducteur.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)