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1. (WO2019066967) FERROELECTRIC CAPACITORS WITH BACKEND TRANSISTORS
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2019/066967 International Application No.: PCT/US2017/054603
Publication Date: 04.04.2019 International Filing Date: 29.09.2017
IPC:
H01L 27/108 (2006.01) ,H01L 21/28 (2006.01) ,H01L 27/24 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
108
Dynamic random access memory structures
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
24
including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
SHARMA, Abhishek A.; US
Agent:
WAGAR, Bruce A.; US
Priority Data:
Title (EN) FERROELECTRIC CAPACITORS WITH BACKEND TRANSISTORS
(FR) CONDENSATEURS FERROÉLECTRIQUES À TRANSISTORS DORSAUX
Abstract:
(EN) An integrated circuit includes a backend thin-film transistor (TFT) a ferroelectric capacitor electrically connected to the backend TFT. The backend TFT has a gate electrode, source and drain regions, a semiconductor region between and physically connecting the source and drain regions, and a gate dielectric between the gate electrode and semiconductor region. The ferroelectric capacitor has a first terminal electrically connected to one of the source and drain regions, a second terminal, and a ferroelectric dielectric between the first and second terminals. In an embodiment, a memory cell includes this integrated circuit, the gate electrode being electrically connected to a wordline, the source region being electrically coupled to a bitline, and the drain region being the one of the source and drain regions. In an embodiment, an embedded memory includes wordlines, bitlines, and a plurality of such memory cells at crossing regions of the wordlines and bitlines.
(FR) La présente invention concerne un circuit intégré qui comprend un transistor à couches minces dorsal (TFT) et un condensateur ferroélectrique connecté électriquement au TFT dorsal. Le TFT dorsal comprend une électrode de grille, des régions de source et de drain, une région semi-conductrice entre les régions de source et de drain et connectant physiquement ces dernières, et un diélectrique de grille entre l'électrode de grille et la région semi-conductrice. Le condensateur ferroélectrique comprend une première borne connectée électriquement à l'une des régions de source et de drain, une seconde borne et un diélectrique ferroélectrique entre les première et seconde bornes. Dans un mode de réalisation, une cellule de mémoire comprend ledit circuit intégré, l'électrode de grille étant électriquement connectée à un canal mot, la région de source étant électriquement couplée à un canal bit, et la région de drain correspondant à la première région de source ou de drain. Dans un mode de réalisation, une mémoire intégrée comprend des canaux mots, des canaux bits et une pluralité de telles cellules de mémoire au niveau des régions de croisement des canaux mots et des canaux bits.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)