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1. (WO2019066966) CMOS CIRCUIT WITH A GROUP III-NITRIDE TRANSISTOR AND METHOD OF PROVIDING SAME
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Pub. No.: WO/2019/066966 International Application No.: PCT/US2017/054601
Publication Date: 04.04.2019 International Filing Date: 29.09.2017
IPC:
H01L 21/8238 (2006.01) ,H01L 27/092 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8238
Complementary field-effect transistors, e.g. CMOS
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
08
including only semiconductor components of a single kind
085
including field-effect components only
088
the components being field-effect transistors with insulated gate
092
complementary MIS field-effect transistors
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Blvd Santa Clara, California 95054, US
Inventors:
RACHMADY, Willy; US
PILLARISETTY, Ravi; US
THEN, Han Wui; US
RADOSAVLJEVIC, Marko; US
DASGUPTA, Sansaptak; US
LE, Van H.; US
Agent:
MILLER, Dermot; US
Priority Data:
Title (EN) CMOS CIRCUIT WITH A GROUP III-NITRIDE TRANSISTOR AND METHOD OF PROVIDING SAME
(FR) CIRCUIT CMOS AVEC UN TRANSISTOR DE NITRURE DU GROUPE III ET SON PROCÉDÉ DE FOURNITURE
Abstract:
(EN) Techniques and mechanisms for providing a complementary metal-oxide-semiconductor (CMOS) circuit which includes a group III-nitride (III-N) material. In an embodiment, an n-type transistor of the CMOS circuit comprises structures which are variously disposed on a group III-N semiconductor material. The n-type transistor is coupled to a p-type transistor of the CMOS circuit, wherein a channel region of the p-type transistor comprises a group III-V semiconductor material. The channel region is configured to conduct current along a first direction, where a surface portion of the group III-N semiconductor material extends along a second direction perpendicular to the second direction. In another embodiment, the group III-N semiconductor material includes a gallium-nitride (GaN) compound, and the group III-V semiconductor material includes a nanopillar of an indium antimonide (InSb) compound.
(FR) L'invention concerne des techniques et des mécanismes permettant de fournir un circuit semi-conducteur à oxyde de métal complémentaire (CMOS) qui comprend un matériau de nitrure du groupe III (III-N). Selon un mode de réalisation, un transistor de type n du circuit CMOS comprend des structures qui sont disposées de diverses manières sur un matériau semi-conducteur du groupe III-N. Le transistor de type n est couplé à un transistor de type p du circuit CMOS, une région de canal du transistor de type p comprenant un matériau semi-conducteur du groupe III-V. La région de canal est configurée pour conduire un courant le long d'une première direction, une partie de surface du matériau semi-conducteur du groupe III-N s'étendant le long d'une seconde direction perpendiculaire à la seconde direction. Selon un autre mode de réalisation, le matériau semi-conducteur du groupe III-N comprend un composé de nitrure de gallium (GaN), et le matériau semi-conducteur du groupe III-V comprend un nanopilier d'un composé d'antimoniure d'indium (InSb).
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)