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1. (WO2019066963) VERTICAL BACKEND TRANSISTOR WITH FERROELECTRIC MATERIAL
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Pub. No.: WO/2019/066963 International Application No.: PCT/US2017/054594
Publication Date: 04.04.2019 International Filing Date: 29.09.2017
IPC:
H01L 27/108 (2006.01) ,H01L 27/11502 (2017.01) ,H01L 49/02 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
108
Dynamic random access memory structures
[IPC code unknown for ERROR IPC Code incorrect: invalid subgroup (0=>999999)!]
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
49
Solid state devices not provided for in groups H01L27/-H01L47/99; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
02
Thin-film or thick-film devices
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Blvd. Santa Clara, CA 95054, US
Inventors:
MORRIS, Daniel H.; US
AVCI, Uygar E.; US
YOUNG, Ian A.; US
Agent:
MUGHAL, Usman A.; US
Priority Data:
Title (EN) VERTICAL BACKEND TRANSISTOR WITH FERROELECTRIC MATERIAL
(FR) TRANSISTOR DE CÔTÉ ARRIÈRE VERTICAL À MATÉRIAU FERROÉLECTRIQUE
Abstract:
(EN) Described is an apparatus which comprises: a word line; a source line; a bit-line; and a memory bit-cell coupled to the source line, the bit-line, and the word line, wherein the memory bit-cell comprises a capacitor including ferroelectric material and a transistor fabricated on a backend of a die.
(FR) L'invention concerne un appareil qui comprend : une ligne de mots ; une ligne de source ; une ligne binaire ; et une cellule binaire de mémoire connectée à la ligne de source, la ligne binaire et la ligne de mots, la cellule binaire de mémoire comprenant un condensateur comprenant un matériau ferroélectrique et un transistor fabriqué sur un côté arrière d'une puce.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)