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1. (WO2019066961) MULTI-LAYER CRYSTALLINE BACK GATED THIN FILM TRANSISTOR
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Pub. No.: WO/2019/066961 International Application No.: PCT/US2017/054589
Publication Date: 04.04.2019 International Filing Date: 29.09.2017
IPC:
H01L 27/108 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
108
Dynamic random access memory structures
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Blvd Santa Clara, California 95054, US
Inventors:
LE, Van H.; US
SHARMA, Abhishek A.; US
DEWEY, Gilbert; US
MILLARD, Kent; US
KAVALIEROS, Jack; US
SHIVARAMAN, Shriram; US
TRONIC, Tristan A.; US
GARDNER, Sanaz; US
WEBER, Justin R.; US
GHANI, Tahir; US
TAN, Li Huey; US
LIN, Kevin; US
Agent:
MUGHAL, Usman; US
Priority Data:
Title (EN) MULTI-LAYER CRYSTALLINE BACK GATED THIN FILM TRANSISTOR
(FR) TRANSISTOR À COUCHES MINCES À GRILLE ARRIÈRE CRISTALLINE MULTICOUCHE
Abstract:
(EN) Described is an apparatus which comprises: a gate comprising a metal; a first layer adjacent to the gate, the first layer comprising a dielectric material; a second layer adjacent to the first layer, the second layer comprising a second material; a third layer adjacent to the second layer, the third layer comprising a third material including an amorphous metal oxide; a fourth layer adjacent to the third layer, the fourth layer comprising a fourth material, wherein the fourth and second materials are different than the third material; a source partially adjacent to the fourth layer; and a drain partially adjacent to the fourth layer.
(FR) L'invention concerne un appareil qui comprend : une grille comprenant un métal ; une première couche adjacente à la grille, la première couche comprenant un matériau diélectrique ; une seconde couche adjacente à la première couche, la seconde couche comprenant un second matériau ; une troisième couche adjacente à la seconde couche, la troisième couche comprenant un troisième matériau comprenant un oxyde métallique amorphe ; une quatrième couche adjacente à la troisième couche, la quatrième couche comprenant un quatrième matériau, les quatrième et second matériaux étant différents du troisième matériau ; une source partiellement adjacente à la quatrième couche ; et un drain partiellement adjacent à la quatrième couche.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)