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1. (WO2019066957) PACKAGE WITH IMPROVED THERMALS
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Pub. No.: WO/2019/066957 International Application No.: PCT/US2017/054584
Publication Date: 04.04.2019 International Filing Date: 29.09.2017
IPC:
H01L 23/367 (2006.01) ,H01L 23/498 (2006.01) ,H01L 23/00 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
36
Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
367
Cooling facilitated by shape of device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
498
Leads on insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Blvd Santa Clara, California 95054, US
Inventors:
EID, Feras; US
SWAN, Johanna; US
Agent:
GUGLIELMI, David; US
Priority Data:
Title (EN) PACKAGE WITH IMPROVED THERMALS
(FR) BOÎTIER AVEC PARAMÈTRES THERMIQUES AMÉLIORÉS
Abstract:
(EN) An apparatus is provided which comprises: a first set of one or more metal pads on a first substrate surface, the first set of one or more metal pads to couple with contacts of an integrated circuit die, a second set of one or more metal pads on the first substrate surface, the second set of one or more metal pads to couple with semiconductor surfaces of the integrated circuit die, one or more thermal regions below the first substrate surface, wherein the one or more thermal regions comprise thermally conductive material and are coupled with the second set of one or more metal pads, dielectric material adjacent the one or more thermal regions, and one or more conductive contacts on a second substrate surface, opposite the first substrate surface, the one or more conductive contacts coupled with the first set of one or more metal pads, and the one or more conductive contacts to couple with contacts of a printed circuit board. Other embodiments are also disclosed and claimed.
(FR) L'invention concerne un appareil qui comprend : un premier ensemble d'un ou de plusieurs plots métalliques sur une première surface de substrat, le premier ensemble d'un ou de plusieurs plots métalliques étant couplé à des contacts d'une puce de circuit intégré, un second ensemble d'un ou de plusieurs plots métalliques sur la première surface de substrat, le second ensemble d'un ou de plusieurs plots métalliques étant couplé avec des surfaces semi-conductrices de la puce de circuit intégré, une ou plusieurs régions thermiques au-dessous de la première surface de substrat, l'une ou plusieurs régions thermiques comprenant un matériau thermoconducteur et étant couplées au second ensemble d'un ou de plusieurs plots métalliques, un matériau diélectrique adjacent à l'un ou plusieurs régions thermiques, et un ou plusieurs contacts conducteurs sur une seconde surface de substrat, opposée à la première surface de substrat, l'un ou plusieurs contacts conducteurs étant couplés au premier ensemble d'un ou de plusieurs plots métalliques, et l'un ou plusieurs contacts conducteurs étant couplés à des contacts d'une carte de circuit imprimé. L'invention se rapporte également à d'autres modes de réalisation.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)