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1. (WO2019066956) INTRA-SEMICONDUCTOR DIE COMMUNICATION VIA WAVEGUIDE IN A MULTI-DIE SEMICONDUCTOR PACKAGE
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Pub. No.: WO/2019/066956 International Application No.: PCT/US2017/054580
Publication Date: 04.04.2019 International Filing Date: 29.09.2017
IPC:
H01P 3/12 (2006.01) ,H01P 5/02 (2006.01) ,H01L 25/065 (2006.01) ,H01L 25/07 (2006.01) ,H01L 23/00 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
P
WAVEGUIDES; RESONATORS, LINES OR OTHER DEVICES OF THE WAVEGUIDE TYPE
3
Waveguides; Transmission lines of the waveguide type
12
Hollow waveguides
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
P
WAVEGUIDES; RESONATORS, LINES OR OTHER DEVICES OF THE WAVEGUIDE TYPE
5
Coupling devices of the waveguide type
02
with invariable factor of coupling
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Blvd Santa Clara, California 95054, US
Inventors:
AYGUN, Kemal; US
QIAN, Zhi Quo; US
XIE, Jian Yong; US
Agent:
CZARNECKI, Michael S.; US
Priority Data:
Title (EN) INTRA-SEMICONDUCTOR DIE COMMUNICATION VIA WAVEGUIDE IN A MULTI-DIE SEMICONDUCTOR PACKAGE
(FR) COMMUNICATION DE PUCE INTRA-SEMI-CONDUCTRICE PAR L'INTERMÉDIAIRE D'UN GUIDE D'ONDES DANS UN BOÎTIER DE SEMI-CONDUCTEUR À PUCES MULTIPLES
Abstract:
(EN) An interposer layer includes an integral waveguide to facilitate high speed (e.g., greater than 80 GHz) communication between semiconductor dies in a semiconductor package. An interposer layer may include a waveguide member and a dielectric layer disposed adjacent at least a portion of an exterior perimeter of the waveguide member. The waveguide member includes a material having a first relative permittivity. The dielectric member includes a material having a second relative permittivity that is less than the first relative permittivity. The waveguide member and the dielectric member form an interposer layer having an upper surface and a lower surface. A first conductive sheet may be disposed proximate the upper surface of the interposer layer and a second conductive sheet may be disposed proximate the lower surface of the interposer layer.
(FR) L'invention concerne une couche d'interposeur comprenant un guide d'ondes intégré pour faciliter une communication à haut débit (par exemple, supérieure à 80 GHz) entre des puces semi-conductrices dans un boîtier de semi-conducteur. Une couche d'interposeur peut comprendre un élément guide d'ondes et une couche diélectrique disposée adjacente à au moins une partie d'un périmètre extérieur de l'élément guide d'ondes. L'élément guide d'ondes comprend un matériau ayant une première permittivité relative. L'élément diélectrique comprend un matériau ayant une seconde permittivité relative qui est inférieure à la première permittivité relative. L'élément guide d'ondes et l'élément diélectrique forment une couche d'interposeur ayant une surface supérieure et une surface inférieure. Une première feuille conductrice peut être disposée à proximité de la surface supérieure de la couche d'interposeur et une seconde feuille conductrice peut être disposée à proximité de la surface inférieure de la couche d'interposeur.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)