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1. (WO2019066953) GROUP III-NITRIDE (III-N) DEVICES WITH REDUCED CONTACT RESISTANCE AND THEIR METHODS OF FABRICATION
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Pub. No.: WO/2019/066953 International Application No.: PCT/US2017/054566
Publication Date: 04.04.2019 International Filing Date: 29.09.2017
IPC:
H01L 29/778 (2006.01) ,H01L 29/78 (2006.01) ,H01L 29/66 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
778
with two-dimensional charge carrier gas channel, e.g. HEMT
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Blvd Santa Clara, California 95054, US
Inventors:
RADOSAVLJEVIC, Marko; US
THEN, Han Wui; US
DASGUPTA, Sansaptak; US
Agent:
HOWARD, James; US
Priority Data:
Title (EN) GROUP III-NITRIDE (III-N) DEVICES WITH REDUCED CONTACT RESISTANCE AND THEIR METHODS OF FABRICATION
(FR) DISPOSITIFS À NITRURE DU GROUPE III (III-N) À RÉSISTANCE DE CONTACT RÉDUITE ET LEURS PROCÉDÉS DE FABRICATION
Abstract:
(EN) A device including a III-N material is described. In an example, the device has a terminal structure with a central body and a first plurality of fins, and a second plurality of fins, opposite the first plurality of fins. A polarization charge inducing layer including a III-N material in the terminal structure. A gate electrode is disposed above and on a portion of the polarization charge inducing layer. A source structure is on the polarization charge inducing layer and on sidewalls of the first plurality of fins. A drain structure is on the polarization charge inducing layer and on sidewalls of the second plurality of fins. The device further includes a source structure and a drain structure on opposite sides of the gate electrode and a source contact on the source structure and a drain contact on the drain structure.
(FR) L'invention concerne un dispositif comprenant un matériau III-N. Dans un exemple, le dispositif présente une structure de borne avec un corps central et une première pluralité d'ailettes, et une deuxième pluralité d'ailettes opposée à la première pluralité d'ailettes. Une couche induisant une charge de polarisation comprend un matériau III-N dans la structure de borne. Une électrode de gâchette est disposée au-dessus et sur une portion de la couche induisant une charge de polarisation. Une structure de source se trouve sur la couche induisant une charge de polarisation et sur les parois latérales de la première pluralité d'ailettes. Une structure de drain se trouve sur la couche induisant une charge de polarisation et sur les parois latérales de la deuxième pluralité d'ailettes. Le dispositif comprend en outre une structure de source et une structure de drain sur des côtés opposés de l'électrode de gâchette et un contact de source sur la structure de source et un contact de drain sur la structure de drain.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)