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1. (WO2019066950) PRINTED WIRING-BOARD ISLANDS FOR CONNECTING CHIP PACKAGES AND METHODS OF ASSEMBLING SAME
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2019/066950 International Application No.: PCT/US2017/054548
Publication Date: 04.04.2019 International Filing Date: 29.09.2017
IPC:
H01L 25/065 (2006.01) ,H01L 25/07 (2006.01) ,H01L 23/00 (2006.01) ,H01L 23/498 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
498
Leads on insulating substrates
Applicants:
SEIDEMANN, Georg [DE/DE]; DE
WAIDHAS, Bernd [DE/DE]; DE
KOLLER, Sonja [DE/DE]; DE
INTEL IP CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
SEIDEMANN, Georg; DE
WAIDHAS, Bernd; DE
KOLLER, Sonja; DE
Agent:
PERDOK, Monique M.; US
ARORA, Suneel / U.S. Reg. No. 42,267; US
BEEKMAN, Marvin / U.S. Reg. No. 38,377; US
BLACK, David W. / U.S. Reg. No. 42,331; US
GOULD, James R. / U.S. Reg. No. 72,086; US
SCHEER, Bradley W. / U.S. Reg. No. 47,059; US
WOO, Justin N. / U.S. Reg. No. 62,686; US
Priority Data:
Title (EN) PRINTED WIRING-BOARD ISLANDS FOR CONNECTING CHIP PACKAGES AND METHODS OF ASSEMBLING SAME
(FR) ÎLOTS DE CARTE DE CIRCUIT IMPRIMÉ POUR CONNECTER DES BOÎTIERS PAVÉS ET LEURS PROCÉDÉS D'ASSEMBLAGE
Abstract:
(EN) A printed wiring-board island relieves added complexity to a printed circuit board. The printed wiring-board island creates an island form factor in the printed circuit board. Coupling of a semiconductive device package to the printed wiring-board island includes a ball-grid array. The ball-grid array can at least partially penetrate the printed wiring-board island.
(FR) Un îlot de carte de circuit imprimé soulage la complexité ajoutée à une carte de circuit imprimé. L'îlot de carte de circuit imprimé crée un facteur de forme d'îlot dans la carte de circuit imprimé. Le couplage d'un boîtier de dispositif à semi-conducteur à l'îlot de carte de circuit imprimé comprend un boîtier matriciel à billes. Le boîtier matriciel à billes peut pénétrer au moins partiellement dans l'îlot de carte de circuit imprimé.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)