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1. (WO2019066944) CHIP WITH MAGNETIC INTERCONNECT ALIGNMENT
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Pub. No.: WO/2019/066944 International Application No.: PCT/US2017/054526
Publication Date: 04.04.2019 International Filing Date: 29.09.2017
IPC:
H01L 23/64 (2006.01) ,H01L 23/12 (2006.01) ,H01L 25/07 (2006.01) ,H01L 25/065 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
58
Structural electrical arrangements for semiconductor devices not otherwise provided for
64
Impedance arrangements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
Applicants:
INTEL CORPORATION [US/US]; US
Inventors:
SWAMINATHAN, Rajasekaran; US
Agent:
PERDOK, Monique M.; US
GOULD, James R., Reg. No. 72,086; US
WOO, Justin N., Reg. No. 62,686; US
BEEKMAN, Marvin L., Reg. No. 38,377; US
ARORA, Suneel, Reg. No. 42,267; US
BIANCHI, Timothy E., Reg. No. 39,610; US
BLACK, David W., Reg. No. 42,331; US
SCHEER, Bradley W., Reg. No. 47,059; US
MCCRACKIN, Ann M., Reg. No. 42,858; US
Priority Data:
Title (EN) CHIP WITH MAGNETIC INTERCONNECT ALIGNMENT
(FR) PUCE À ALIGNEMENT D'INTERCONNEXION MAGNÉTIQUE
Abstract:
(EN) An electronic assembly, and a method for making the electronic assembly, includes a first electronic component, a second electronic component, and a plurality of interconnects. The plurality of interconnects electrically couple the first electronic component to the second electronic component. Each of the plurality of interconnects comprise one of a plurality of first magnetic components in physical alignment with an associated one of a plurality of second magnetic components, the plurality of second magnetic components being components of one of the second electronic component and the plurality of interconnects.
(FR) Un ensemble électronique, et un procédé de fabrication de l'ensemble électronique, comprennent un premier composant électronique, un second composant électronique et une pluralité d'interconnexions. La pluralité d'interconnexions couplent électriquement le premier composant électronique au second composant électronique. Chaque interconnexion de la pluralité d'interconnexions comprend un composant parmi une pluralité de premiers composants magnétiques en alignement physique avec un composant associé parmi une pluralité de seconds composants magnétiques, la pluralité de seconds composants magnétiques étant des composants du second composant électronique ou de la pluralité d'interconnexions.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)