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1. (WO2019066943) SEMICONDUCTOR PACKAGES WITH EMBEDDED INTERCONNECTS
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Pub. No.: WO/2019/066943 International Application No.: PCT/US2017/054524
Publication Date: 04.04.2019 International Filing Date: 29.09.2017
IPC:
H01L 23/522 (2006.01) ,H01L 23/48 (2006.01) ,H01L 23/498 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
498
Leads on insulating substrates
Applicants:
LEE, Kyu Oh [KR/US]; US
SENEVIRATNE, Dilan [LK/US]; US
ELURI, Ravindranadh T. [IN/US]; US
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
LEE, Kyu Oh; US
SENEVIRATNE, Dilan; US
ELURI, Ravindranadh T.; US
Agent:
WOO, Justin N.; US
ARORA, Suneel / U.S. Reg. No. 42,267; US
BEEKMAN, Marvin / U.S. Reg. No. 38,377; US
BLACK, David W. / U.S. Reg. No. 42,331; US
GOULD, James R. / U.S. Reg. No. 72,086; US
PERDOK, Monique M. / U.S. Reg. No. 42,989; US
SCHEER, Bradley W. / U.S. Reg. No. 47,059; US
Priority Data:
Title (EN) SEMICONDUCTOR PACKAGES WITH EMBEDDED INTERCONNECTS
(FR) BOÎTIERS DE SEMI-CONDUCTEUR DOTÉS D'INTERCONNEXIONS INTÉGRÉES
Abstract:
(EN) A semiconductor package may include a semiconductor package first side, an embedded bridge interconnect, a first via, and a second via. The bridge interconnect may include a bridge interconnect first side with a conductive pad and a bridge interconnect second side. The distance between the bridge interconnect first side and the semiconductor package first side may be less than a distance between the bridge interconnect second side and the semiconductor package first side. The first and second vias may each include a first end that is narrower than s second end. The semiconductor package first side may be closer to the first end of the first via than the second end of the first via, and closer to the second end of the second via than the first end of the second via. The first side of the semiconductor package may be configured to electrically couple to a die.
(FR) L'invention concerne un boîtier de semi-conducteur pouvant comprendre un premier côté de boîtier de semi-conducteur, une interconnexion en pont intégrée, un premier trou de raccordement et un second trou de raccordement. L'interconnexion en pont peut comprendre un premier côté d'interconnexion en pont doté d'une pastille conductrice et un second côté d'interconnexion en pont. La distance entre le premier côté d'interconnexion en pont et le premier côté de boîtier de semi-conducteurs peut être inférieure à une distance entre le second côté d'interconnexion en pont et le premier côté de boîtier de semi-conducteurs. Les premier et second trous de raccordement peuvent individuellement comprendre une première extrémité qui est plus étroite que la seconde extrémité. Le premier côté du boîtier de semi-conducteur peut être plus proche de la première extrémité du premier trou de raccordement que de la seconde extrémité du premier trou de raccordement, et plus proche de la seconde extrémité du second trou de raccordement que de la première extrémité du second trou de raccordement. Le premier côté du boîtier de semi-conducteur peut être conçu pour être couplé électriquement à une puce.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)