Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2019066926) SPACER-PATTERNED INVERTERS BASED ON THIN-FILM TRANSISTORS
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2019/066926 International Application No.: PCT/US2017/054413
Publication Date: 04.04.2019 International Filing Date: 29.09.2017
IPC:
H01L 29/786 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
Applicants:
SHARMA, Abhishek A. [IN/US]; US
LE, Van H. [US/US]; US
DEWEY, Gilbert [US/US]; US
RACHMADY, Willy [ID/US]; US
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
SHARMA, Abhishek A.; US
LE, Van H.; US
DEWEY, Gilbert; US
RACHMADY, Willy; US
Agent:
WANG, Yuke; US
PUGH, Joseph A.; US
COFIELD, Michael A.; US
BLANK, Eric S.; US
ROJO, Estiven; US
BRASK, Justin K.; US
AUYEUNG, Al; US
BERNADICOU, Michael A.; US
BLAIR, Steven R.; US
DANSKIN, Timothy A.; US
HALEVA, Aaron S.; US
MAKI, Nathan R.; US
MARLINK, Jeffrey S.; US
MOORE, Michael S.; US
PARKER, Wesley E.; US
RASKIN, Vladimir; US
STRAUSS, Ryan N.; US
YATES, Steven D.; US
SULLIVAN, Stephen G.; US
Priority Data:
Title (EN) SPACER-PATTERNED INVERTERS BASED ON THIN-FILM TRANSISTORS
(FR) ONDULEURS À MOTIFS D'ÉLÉMENTS D'ESPACEMENT BASÉS SUR DES TRANSISTORS EN COUCHES MINCES
Abstract:
(EN) A semiconductor device may include a first gate electrode and a second gate electrode. A first channel area and a second channel area may be above the first gate electrode, where the first channel area may include a first type channel material, and the second channel area may include a second type channel material. A third channel area and a fourth channel area may be above the second gate electrode, where the third channel area may include the first type channel material, and the fourth channel area may include the second type channel material. The third channel area may be separated from the first channel area by a spacer. An inverter may include the first gate electrode, the first channel area, and the second channel area, while another inverter may include the second gate electrode, the third channel area, and the fourth channel area. Other embodiments may be described/claimed.
(FR) L’invention concerne un dispositif semi-conducteur pouvant comprendre une première électrode grille et une seconde électrode grille. Une première zone de canal et une seconde zone de canal peuvent être au-dessus de la première électrode grille, la première zone de canal pouvant comprendre un matériau de canal de premier type, et la seconde zone de canal pouvant comprendre un matériau de canal de second type. Une troisième zone de canal et une quatrième zone de canal peuvent être au-dessus de la deuxième électrode grille, la troisième zone de canal pouvant comprendre le matériau de canal de premier type, et la quatrième zone de canal pouvant comprendre le matériau de canal de second type. La troisième zone de canal peut être séparée de la première zone de canal par un élément d'espacement. Un onduleur peut comprendre la première électrode grille, la première zone de canal et la seconde zone de canal, tandis qu'un autre onduleur peut comprendre la deuxième électrode grille, la troisième zone de canal et la quatrième zone de canal. L'invention concerne également d'autres modes de réalisation.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)