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1. (WO2019066922) PACKAGE ON PACKAGE ASSEMBLY
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Pub. No.: WO/2019/066922 International Application No.: PCT/US2017/054391
Publication Date: 04.04.2019 International Filing Date: 29.09.2017
IPC:
H01L 25/07 (2006.01) ,H01L 23/498 (2006.01) ,H01L 23/00 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
498
Leads on insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
KIM, Hyoung Il; US
Agent:
BLAIR, Steven R.; US
AUYEUNG, Al; US
BERNADICOU, Michael A.; US
BLANK, Eric S.; US
BRASK, Justin K.; US
COFIELD, Michael A.; US
COWGER, Graciela G.; US
DANSKIN, Timothy A.; US
FORD, Stephen S.; US
HALEVA, Aaron S.; US
MAKI, Nathan R.; US
MARLINK, Jeffrey S.; US
MOORE, Michael S.; US
PARKER, Wesley E.; US
RASKIN, Vladimir; US
STRAUSS, Ryan N.; US
WANG, Yuke; US
YATES, Steven D.; US
Priority Data:
Title (EN) PACKAGE ON PACKAGE ASSEMBLY
(FR) BOÎTIER ET ASSEMBLAGE DE BOÎTIER
Abstract:
(EN) Embodiments herein relate to a package-on-package assembly that may include a first package with the first side coupled to a printed circuit board (PCB) and a second side opposite the first side, a second package coupled with the second side of the first package, where the second package is a leadframe package with one or more leads coupled with the PCB, where the first package and the second package are electrically coupled through the PCB. Other embodiments may be described and/or claimed.
(FR) Des modes de réalisation de la présente invention concernent un assemblage de boîtier sur boîtier qui peut comprendre un premier boîtier dont le premier côté est couplé à une carte à circuit imprimé (PCB) et un deuxième côté opposé au premier côté, un deuxième boîtier couplé au deuxième côté du premier boîtier, le deuxième boîtier étant un boîtier de grille de connexion comprenant un ou plusieurs conducteurs reliés à la PCB, le premier boîtier et le deuxième boîtier étant reliés électriquement à travers la PCB. L'invention peut également concerner d'autres modes de réalisation.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)