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1. (WO2019066906) SRAM USING 2T-2S
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Pub. No.: WO/2019/066906 International Application No.: PCT/US2017/054330
Publication Date: 04.04.2019 International Filing Date: 29.09.2017
IPC:
G11C 11/417 (2006.01) ,H01L 27/11 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21
using electric elements
34
using semiconductor devices
40
using transistors
41
forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
413
Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
417
for memory cells of the field-effect type
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
11
Static random access memory structures
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
SHARMA, Abhishek A.; US
DOYLE, Brian S.; US
PILLARISETTY, Ravi; US
MAJHI, Prashant; US
Agent:
MALONEY, Neil F.; US
Priority Data:
Title (EN) SRAM USING 2T-2S
(FR) SRAM UTILISANT DES 2T-2S
Abstract:
(EN) A 2T-2S SRAM cell exhibiting a complementary scheme, that includes two selector devices that exhibit negative differential resistance. Advantages include lower area and better performance than traditional SRAM cells, according to some embodiments. The term 1T-1S refers to a transistor in series with a selector device. Accordingly, the term 2T-2S refers to two such 1T-1S structures.
(FR) L'invention concerne une cellule SRAM 2T-2S présentant un schéma complémentaire, qui comprend deux dispositifs de sélection qui présentent une résistance différentielle négative. Les avantages comprennent une zone inférieure et une meilleure performance que les cellules SRAM classiques, selon certains modes de réalisation. Le terme 1T-1S se réfère à un transistor en série avec un dispositif sélecteur. Par conséquent, le terme 2T-2S se réfère à deux de ces structures 1T-1S.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)