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1. (WO2019066903) MEMORY SHAPE ALLOY INTERCONNECT
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Pub. No.: WO/2019/066903 International Application No.: PCT/US2017/054317
Publication Date: 04.04.2019 International Filing Date: 29.09.2017
IPC:
H01L 23/40 (2006.01) ,H01L 23/00 (2006.01) ,H01L 23/367 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
40
Mountings or securing means for detachable cooling or heating arrangements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
36
Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
367
Cooling facilitated by shape of device
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
LAI, Min-Tih; US
KIM, Hyoung Il; US
Agent:
MARLINK, Jeffrey S.; US
AUYEUNG, Al; US
BERNADICOU, Michael A.; US
BLAIR, Steven R.; US
BLANK, Eric S.; US
BRASK, Justin K.; US
COFIELD, Michael A.; US
COWGER, Graciela G.; US
DANSKIN, Timothy A.; US
FORD, Stephen S.; US
HALEVA, Aaron S.; US
MAKI, Nathan R.; US
MOORE, Michael S.; US
PARKER, Wesley E.; US
RASKIN, Vladimir; US
STRAUSS, Ryan N.; US
WANG, Yuke; US
YATES, Steven D.; US
Priority Data:
Title (EN) MEMORY SHAPE ALLOY INTERCONNECT
(FR) INTERCONNEXION EN ALLIAGE À MÉMOIRE DE FORME
Abstract:
(EN) Herein described are apparatuses, systems, and methods related to an interconnect formed of a memory shape alloy for a semiconductor package. A semiconductor device may include a semiconductor package with a contact and an interconnect coupled to the contact of the semiconductor package. The interconnect may be formed of a memory shape alloy and may be to couple the semiconductor package to a printed circuit board (PCB). Other embodiments may be described and/or claimed.
(FR) La présente invention concerne des appareils, des systèmes et des procédés se rapportant à une interconnexion formée d'un alliage à mémoire de forme pour un boîtier de semiconducteur. Un dispositif semiconducteur peut comprendre un boîtier de semiconducteur muni d'un contact et d'une interconnexion reliée au contact du boîtier de semiconducteur. L'interconnexion peut être formée d'un alliage à mémoire de forme et peut être destinée à relier le boîtier de semiconducteur à une carte à circuit imprimé (PCB). L'invention peut également concerner d'autres modes de réalisation.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)