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1. (WO2019066902) PILLAR ARRAY PLATE
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Pub. No.: WO/2019/066902 International Application No.: PCT/US2017/054315
Publication Date: 04.04.2019 International Filing Date: 29.09.2017
IPC:
H01L 23/538 (2006.01) ,H01L 25/07 (2006.01) ,H01L 23/12 (2006.01) ,H01L 23/522 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
538
the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
Applicants:
YONG, Khang Choong [MY/MY]; MY
LIM, Min Suet [MY/MY]; MY
GOH, Eng Huat [MY/MY]; MY
SONG, Wil Choon [MY/MY]; MY
KOH, Boon Ping [MY/MY]; MY
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
YONG, Khang Choong; MY
LIM, Min Suet; MY
GOH, Eng Huat; MY
SONG, Wil Choon; MY
KOH, Boon Ping; MY
Agent:
BABBITT, William Thomas; US
VINCENT, Lester J.; US
Priority Data:
Title (EN) PILLAR ARRAY PLATE
(FR) PLAQUETTE À RÉSEAU DE PILIERS
Abstract:
(EN) An integrated circuit assembly including a package; a printed circuit board; and an interface between the package and the printed circuit board, wherein the interface includes a body including a plurality of openings therethrough and with electrically conductive material in ones of the plurality of openings defining interface contact points on opposite sides of the body, the contact points coupled to contact points on the package and the printed circuit board. A method of forming an integrated circuit assembly including positioning an interface between an integrated circuit package and a substrate, wherein the interface includes a body including a plurality of openings therethrough and with electrically conductive material in ones of the plurality of openings defining interface contact points on opposite sides of the body of the interface; coupling the interface contact points to respective ones of contacts points on the integrated circuit package and on the substrate.
(FR) L'invention concerne un ensemble circuit intégré comprenant un boîtier ; une carte de circuit imprimé ; et une interface entre le boîtier et la carte de circuit imprimé, l'interface comprenant un corps comprenant une pluralité d'ouvertures à travers celui-ci et avec un matériau électroconducteur dans certaines ouvertures de la pluralité d'ouvertures définissant des points de contact d'interface sur des côtés opposés du corps, les points de contact étant couplés à des points de contact sur le boîtier et la carte de circuit imprimé. L'invention concerne également un procédé de formation d'un ensemble circuit intégré consistant à positionner une interface entre un boîtier de circuit intégré et un substrat, l'interface comprenant un corps comprenant une pluralité d'ouvertures à travers celui-ci et avec un matériau électroconducteur dans certaines ouvertures de la pluralité d'ouvertures définissant des points de contact d'interface sur des côtés opposés du corps de l'interface ; à coupler les points de contact d'interface à des points de contact respectifs sur le boîtier de circuit intégré et sur le substrat.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)