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1. (WO2019066901) A NOVEL MODULAR TECHNIQUE FOR DIE-LEVEL LIQUID COOLING
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Pub. No.: WO/2019/066901 International Application No.: PCT/US2017/054305
Publication Date: 04.04.2019 International Filing Date: 29.09.2017
IPC:
H01L 23/46 (2006.01) ,H01L 23/40 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
46
involving the transfer of heat by flowing fluids
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
40
Mountings or securing means for detachable cooling or heating arrangements
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
JHA, Chandra M.; US
CHANG, Je-Young; US
Agent:
BABBITT, William Thomas; US
VINCENT, Lester J.; US
Priority Data:
Title (EN) A NOVEL MODULAR TECHNIQUE FOR DIE-LEVEL LIQUID COOLING
(FR) NOUVELLE TECHNIQUE MODULAIRE DE REFROIDISSEMENT DE LIQUIDE AU NIVEAU DE LA PUCE
Abstract:
(EN) An integrated circuit assembly including a first die including a device side and a backside opposite the device side; and a second die including a plurality of fluidly accessible channels therein, wherein the second die is coupled to a backside of the first die. A method of fabricating an integrated circuit assembly including coupling a first die to a second die, wherein the first die includes a device side and an opposite backside, wherein the device side includes a plurality of integrated circuits and wherein the second die includes a plurality of fluidly accessible channels therein.
(FR) L'invention concerne un ensemble circuit intégré comprenant une première puce possédant un côté dispositif et un côté arrière situé à l'opposé du côté dispositif ; et une seconde puce comportant en son sein une pluralité de canaux accessibles de manière fluidique, la seconde puce étant accouplée à un côté arrière de la première puce. Un procédé de fabrication d'un ensemble circuit intégré consiste à accoupler une première puce et une seconde puce, la première puce possédant un côté dispositif et un côté arrière situé à l'opposé, le côté dispositif comportant une pluralité de circuits intégrés et la seconde puce comprenant en son sein une pluralité de canaux accessibles de manière fluidique.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)