Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2019066893) 2S-1C 4F2 CROSS-POINT DRAM ARRAY
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2019/066893 International Application No.: PCT/US2017/054276
Publication Date: 04.04.2019 International Filing Date: 29.09.2017
IPC:
H01L 27/108 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
108
Dynamic random access memory structures
Applicants:
PILLARISETTY, Ravi [US/US]; US
SHARMA, Abhishek A. [IN/US]; US
MAJHI, Prashant [IN/US]; US
KARPOV, Elijah V. [US/US]; US
DOYLE, Brian S. [IE/US]; US
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
PILLARISETTY, Ravi; US
SHARMA, Abhishek A.; US
MAJHI, Prashant; US
KARPOV, Elijah V.; US
DOYLE, Brian S.; US
Agent:
SULLIVAN, Stephen G.; US
BRASK, Justin K.; US
AUYEUNG, Al; US
BERNADICOU, Michael A.; US
BLAIR, Steven R.; US
BLANK, Eric S.; US
COFIELD, Michael A.; US
DANSKIN, Timothy A.; US
HALEVA, Aaron S.; US
MAKI, Nathan R.; US
MARLINK, Jeffrey S.; US
MOORE, Michael S.; US
PARKER, Wesley E.; US
PUGH, Joseph A.; US
RASKIN, Vladimir; US
STRAUSS, Ryan N.; US
WANG, Yuke; US
YATES, Steven D.; US
ROJO, Estiven; US
Priority Data:
Title (EN) 2S-1C 4F2 CROSS-POINT DRAM ARRAY
(FR) MATRICE DE MÉMOIRE DRAM À POINTS DE CROISEMENT 2S-1C 4F2
Abstract:
(EN) A memory device comprises a first selector and a storage capacitor in series with the first selector. A second selector is in parallel with the storage capacitor coupled between the first selector and zero volts. A plurality of memory devices form a 2S-1C cross-point DRAM array with 4F2 or less density.
(FR) Un dispositif de mémoire comprend un premier sélecteur et un condensateur de stockage en série avec le premier sélecteur. Un second sélecteur est en parallèle avec le condensateur de stockage couplé entre le premier sélecteur et zéro volt. Une pluralité de dispositifs de mémoire forment un réseau DRAM à points de croisement 2S-1C avec 4F2 ou une densité moindre.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)