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1. (WO2019066884) SEMICONDUCTOR PACKAGES, AND METHODS FOR FORMING SEMICONDUCTOR PACKAGES
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Pub. No.: WO/2019/066884 International Application No.: PCT/US2017/054209
Publication Date: 04.04.2019 International Filing Date: 29.09.2017
IPC:
H01L 25/065 (2006.01) ,H01L 23/498 (2006.01) ,H01L 23/00 (2006.01) ,H01L 23/538 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
498
Leads on insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
538
the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
Applicants:
INTEL IP CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, CA 95054, US
Inventors:
WAIDHAS, Bernd; DE
SEIDEMANN, Georg; DE
WAGNER, Thomas; DE
WOLTER, Andreas; DE
AUGUSTIN, Andreas; DE
KOLLER, Sonja; DE
ORT, Thomas; DE
MAHNKOPF, Reinhard; DE
Agent:
ARABI, Mani; DE
Priority Data:
Title (EN) SEMICONDUCTOR PACKAGES, AND METHODS FOR FORMING SEMICONDUCTOR PACKAGES
(FR) BOÎTIERS DE SEMI-CONDUCTEUR ET PROCÉDÉS DE FORMATION DE BOÎTIERS DE SEMI-CONDUCTEUR
Abstract:
(EN) A semiconductor package includes a first semiconductor die, a semiconductor device comprising a second semiconductor die, and one or more wire bond structures. The wire bond structure includes a bond interface portion. The wire bond structure is arranged next to the first semiconductor die. The first semiconductor die and the bond interface portion of the wire bond structure are arranged at the same side of the semiconductor device. An interface contact structure of the semiconductor device is electrically connected to the wire bond structure.
(FR) L'invention concerne un boîtier de semi-conducteur qui comprend une première puce de semi-conducteur, un dispositif à semi-conducteur comprenant une seconde puce de semi-conducteur, et une ou plusieurs structures de connexion par fil. La structure de connexion par fil comprend une partie interface de connexion. La structure de connexion par fil est agencée à côté de la première puce de semi-conducteur. La première puce de semi-conducteur et la partie interface de connexion de la structure de connexion par fil sont disposées du même côté du dispositif à semi-conducteur. Une structure de contact d'interface du dispositif à semi-conducteur est électriquement connectée à la structure de connexion par fil.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)