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1. (WO2019066880) GROUP III-V SEMICONDUCTOR DEVICES HAVING ASYMMETRIC SOURCE AND DRAIN STRUCTURES
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2019/066880 International Application No.: PCT/US2017/054193
Publication Date: 04.04.2019 International Filing Date: 28.09.2017
IPC:
H01L 29/78 (2006.01) ,H01L 29/423 (2006.01) ,H01L 29/66 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
423
not carrying the current to be rectified, amplified or switched
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
MA, Sean T. [US/US]; US
DEWEY, Gilbert [US/US]; US
RACHMADY, Willy [ID/US]; US
KENNEL, Harold W. [US/US]; US
HUANG, Cheng-Ying; US
METZ, Matthew V. [US/US]; US
MINUTILLO, Nicholas G. [US/US]; US
KAVALIEROS, Jack T. [US/US]; US
MURTHY, Anand S. [US/US]; US
Inventors:
MA, Sean T.; US
DEWEY, Gilbert; US
RACHMADY, Willy; US
KENNEL, Harold W.; US
HUANG, Cheng-Ying; US
METZ, Matthew V.; US
MINUTILLO, Nicholas G.; US
KAVALIEROS, Jack T.; US
MURTHY, Anand S.; US
Agent:
BRASK, Justin K.; US
AUYEUNG, Al; US
BERNADICOU, Michael A.; US
BLAIR, Steven R.; US
BLANK, Eric S.; US
COFIELD, Michael A.; US
DANSKIN, Timothy A.; US
HALEVA, Aaron S.; US
MAKI, Nathan R.; US
MARLINK, Jeffrey S.; US
MOORE, Michael S.; US
PARKER, Wesley E.; US
PUGH, Joseph A.; US
RASKIN, Vladimir; US
STRAUSS, Ryan N.; US
WANG, Yuke; US
YATES, Steven D.; US
SULLIVAN, Stephen G.; US
ROJO, Estiven; US
Priority Data:
Title (EN) GROUP III-V SEMICONDUCTOR DEVICES HAVING ASYMMETRIC SOURCE AND DRAIN STRUCTURES
(FR) DISPOSITIFS À SEMI-CONDUCTEUR DU GROUPE III-V AYANT DES STRUCTURES DE SOURCE ET DE DRAIN ASYMÉTRIQUES
Abstract:
(EN) Group III-V semiconductor devices having asymmetric source and drain structures and their methods of fabrication are described. In an example, an integrated circuit structure includes a gallium arsenide layer on a substrate. A channel structure is on the gallium arsenide layer. The channel structure includes indium, gallium and arsenic. A source structure is at a first end of the channel structure and a drain structure is at a second end of the channel structure. The drain structure has a wider band gap than the source structure. A gate structure is over the channel structure.
(FR) L'invention porte sur des dispositifs à semi-conducteur du groupe III-V ayant des structures de source et de drain asymétriques, et sur leurs procédés de fabrication. Dans un exemple, une structure de circuit intégré comprend une couche d'arséniure de gallium sur un substrat. Une structure de canal se trouve sur la couche d'arséniure de gallium. La structure de canal comprend de l'indium, du gallium et de l'arsenic. Une structure de source se trouve à une première extrémité de la structure de canal et une structure de drain se trouve à une seconde extrémité de la structure de canal. La structure de drain a une bande interdite plus large que celle de la structure de source. Une structure de grille se trouve au-dessus de la structure de canal.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)