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1. (WO2019066879) GROUP III-V SEMICONDUCTOR FUSES AND THEIR METHODS OF FABRICATION
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Pub. No.: WO/2019/066879 International Application No.: PCT/US2017/054185
Publication Date: 04.04.2019 International Filing Date: 28.09.2017
IPC:
H01L 23/525 (2006.01) ,H01L 23/62 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
525
with adaptable interconnections
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
58
Structural electrical arrangements for semiconductor devices not otherwise provided for
62
Protection against overcurrent or overload, e.g. fuses, shunts
Applicants:
THEN, Han Wui [MY/US]; US
RADOSAVLJEVIC, Marko [US/US]; US
DASGUPTA, Sansaptak [IN/US]; US
TRONIC, Tristan A. [US/US]; US
PAUL, Rajat K. [BD/US]; US
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
THEN, Han Wui; US
RADOSAVLJEVIC, Marko; US
DASGUPTA, Sansaptak; US
TRONIC, Tristan A.; US
PAUL, Rajat K.; US
Agent:
BERNADICOU, Michael A.; US
AUYEUNG, Al; US
BLAIR, Steven R.; US
BLANK, Eric S.; US
BRASK, Justin K.; US
COFIELD, Michael A.; US
DANSKIN, Timothy A.; US
GARTHWAITE, Martin S.; US
HALEVA, Aaron S.; US
MAKI, Nathan R.; US
MARLINK, Jeffrey S.; US
MOORE, Michael S.; US
PARKER, Wesley E.; US
PUGH, Joseph A.; US
RASKIN, Vladimir; US
STRAUSS, Ryan N.; US
WANG, Yuke; US
YATES, Steven D.; US
Priority Data:
Title (EN) GROUP III-V SEMICONDUCTOR FUSES AND THEIR METHODS OF FABRICATION
(FR) FUSIBLES SEMI-CONDUCTEUR DU GROUPE III-N ET LEURS PROCÉDÉS DE FABRICATION
Abstract:
(EN) Group III-V semiconductor fuses and their methods of fabrication are described. In an example, a fuse includes a gallium nitride layer on a substrate. An oxide layer is disposed in a trench in the gallium nitride layer. A first contact is on the gallium nitride layer on a first side of the trench, the first contact comprising indium, gallium and nitrogen. A second contact is on the gallium nitride layer on a second side of the trench, the second side opposite the first side, the second contact comprising indium, gallium and nitrogen. A filament is over the oxide layer in the trench, the filament coupled to the first contact and to the second contact wherein the filament comprises indium, gallium and nitrogen.
(FR) L'invention concerne des fusibles semi-conducteur du groupe III-V et leurs procédés de fabrication. Dans un exemple, un fusible comprend une couche de nitrure de gallium sur un substrat. Une couche d'oxyde est disposée dans une tranchée dans la couche de nitrure de gallium. Un premier contact est sur la couche de nitrure de gallium sur un premier côté de la tranchée, le premier contact comprenant de l'indium, du gallium et de l'azote. Un second contact est sur la couche de nitrure de gallium sur un second côté de la tranchée, le second côté étant opposé au premier côté, le second contact comprenant de l'indium, du gallium et de l'azote. Un filament est sur la couche d'oxyde dans la tranchée, le filament étant couplé au premier contact et au second contact, le filament comprenant de l'indium, du gallium et de l'azote.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)