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1. (WO2019066877) GALLIUM NITRIDE TRANSISTORS WITH DRAIN FIELD PLATES AND THEIR METHODS OF FABRICATION
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Pub. No.: WO/2019/066877 International Application No.: PCT/US2017/054173
Publication Date: 04.04.2019 International Filing Date: 28.09.2017
IPC:
H01L 29/778 (2006.01) ,H01L 29/423 (2006.01) ,H01L 29/78 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
778
with two-dimensional charge carrier gas channel, e.g. HEMT
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
423
not carrying the current to be rectified, amplified or switched
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
Applicants:
THEN, Han Wui [MY/US]; US
LEUSCHNER, Stephan [DE/DE]; DE
RADOSAVLJEVIC, Marko [US/US]; US
DASGUPTA, Sansaptak [IN/US]; US
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
THEN, Han Wui; US
LEUSCHNER, Stephan; DE
RADOSAVLJEVIC, Marko; US
DASGUPTA, Sansaptak; US
Agent:
BERNADICOU, Michael A.; US
AUYEUNG, Al; US
BLAIR, Steven R.; US
BLANK, Eric S.; US
BRASK, Justin K.; US
COFIELD, Michael A.; US
DANSKIN, Timothy A.; US
GARTHWAITE, Martin S.; US
HALEVA, Aaron S.; US
MAKI, Nathan R.; US
MARLINK, Jeffrey S.; US
MOORE, Michael S.; US
PARKER, Wesley E.; US
PUGH, Joseph A.; US
RASKIN, Vladimir; US
STRAUSS, Ryan N.; US
WANG, Yuke; US
YATES, Steven D.; US
Priority Data:
Title (EN) GALLIUM NITRIDE TRANSISTORS WITH DRAIN FIELD PLATES AND THEIR METHODS OF FABRICATION
(FR) TRANSISTORS AU NITRURE DE GALLIUM AVEC PLAQUES DE CHAMP DE DRAIN ET LEURS PROCÉDÉS DE FABRICATION
Abstract:
(EN) Gallium nitride (GaN) transistors with drain field plates and their methods of fabrication are described. In an example, a transistor includes a gallium nitride (GaN) layer above a substrate, a gate structure over the GaN layer, a source region on a first side of the gate structure, a drain region on a second side of the gate structure, the second side opposite the first side, and a drain field plate above the drain region, wherein the drain field plate is not electrically coupled to the gate structure or the source region.
(FR) L'invention concerne des transistors au nitrure de gallium (GaN) comprenant des plaques de champ de drain et leurs procédés de fabrication. Dans un exemple, un transistor comprend une couche de nitrure de gallium (GaN) au-dessus d'un substrat, une structure de gâchette sur la couche de GaN, une région de source sur un premier côté de la structure de gâchette, une région de drain sur un deuxième côté de la structure de gâchette, le deuxième côté étant opposé au premier côté, et une plaque de champ de drain au-dessus de la région de drain, la plaque de champ de drain n'étant pas reliée électriquement à la structure de gâchette ou à la région de source.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)