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1. (WO2019066871) GALLIUM NITRIDE TRANSISTORS WITH MULTIPLE THRESHOLD VOLTAGES AND THEIR METHODS OF FABRICATION
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Pub. No.: WO/2019/066871 International Application No.: PCT/US2017/054137
Publication Date: 04.04.2019 International Filing Date: 28.09.2017
IPC:
H01L 29/778 (2006.01) ,H01L 29/78 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
778
with two-dimensional charge carrier gas channel, e.g. HEMT
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
Applicants:
THEN, Han Wui [MY/US]; US
DASGUPTA, Sansaptak [IN/US]; US
RADOSAVLJEVIC, Marko [US/US]; US
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
THEN, Han Wui; US
DASGUPTA, Sansaptak; US
RADOSAVLJEVIC, Marko; US
Agent:
BERNADICOU, Michael A.; US
AUYEUNG, Al; US
BLAIR, Steven R.; US
BLANK, Eric S.; US
BRASK, Justin K.; US
COFIELD, Michael A.; US
DANSKIN, Timothy A.; US
GARTHWAITE, Martin S.; US
HALEVA, Aaron S.; US
MAKI, Nathan R.; US
MARLINK, Jeffrey S.; US
MOORE, Michael S.; US
PARKER, Wesley E.; US
PUGH, Joseph A.; US
RASKIN, Vladimir; US
STRAUSS, Ryan N.; US
WANG, Yuke; US
YATES, Steven D.; US
Priority Data:
Title (EN) GALLIUM NITRIDE TRANSISTORS WITH MULTIPLE THRESHOLD VOLTAGES AND THEIR METHODS OF FABRICATION
(FR) TRANSISTORS AU NITRURE DE GALLIUM À MULTIPLES TENSIONS DE SEUIL ET LEURS PROCÉDÉS DE FABRICATION
Abstract:
(EN) Gallium nitride transistors having multiple threshold voltages are described. In an example, a transistor includes a gallium nitride layer over a substrate, a gate stack over the gallium nitride layer, a source region on a first side of the gate stack, and a drain region on a second side of the gate stack, the second side opposite the first side, wherein the gate stack has a gate length in a first direction extending from the source region to the drain region, the gate stack having a gate width in a second direction perpendicular to the first direction and parallel to the source region and the drain region. The transistor also includes a polarization layer beneath the gate stack and on the GaN layer, the polarization layer having a first portion having a first thickness under a first gate portion and a second thickness under a second gate portion.
(FR) L'invention concerne des transistors au nitrure de gallium ayant de multiples tensions de seuil. Dans un exemple, un transistor comprend une couche de nitrure de gallium sur un substrat, un empilement de grille sur la couche de nitrure de gallium, une région de source sur un premier côté de l'empilement de grille, et une région de drain sur un second côté de l'empilement de grille, le second côté opposé au premier côté, l'empilement de grille ayant une longueur de grille dans une première direction s'étendant de la région de source à la région de drain, l'empilement de grille ayant une largeur de grille dans une seconde direction perpendiculaire à la première direction et parallèle à la région de source et à la région de drain. Le transistor comprend également une couche de polarisation sous l'empilement de grille et sur la couche de GaN, la couche de polarisation ayant une première partie ayant une première épaisseur sous une première partie de grille et une seconde épaisseur sous une seconde partie de grille.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)