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1. (WO2019066870) FARADAY CAGE COMPRISING THROUGH-SILICON-VIAS
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Pub. No.: WO/2019/066870 International Application No.: PCT/US2017/054111
Publication Date: 04.04.2019 International Filing Date: 28.09.2017
IPC:
H01L 23/60 (2006.01) ,H01L 23/52 (2006.01) ,H01L 25/065 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
58
Structural electrical arrangements for semiconductor devices not otherwise provided for
60
Protection against electrostatic charges or discharges, e.g. Faraday shields
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Blvd. Santa Clara, California 95054, US
Inventors:
BHARATH, Krishna; US
RADHAKRISHNAN, Kaladhar; US
LAMBERT, William; US
HILL, Michael; US
CHOI, Beomseok; US
Agent:
MUGHAL, Usman A.; US
Priority Data:
Title (EN) FARADAY CAGE COMPRISING THROUGH-SILICON-VIAS
(FR) CAGE DE FARADAY COMPRENANT DES TROUS D'INTERCONNEXION TRAVERSANT LE SILICIUM
Abstract:
(EN) An apparatus is provided which comprises: a substrate; a die coupled to the substrate; at least two active devices positioned in the substrate; a plurality of vias surrounding at least one of the two active devices such that a Faraday cage is formed around the at least one of the two active devices.
(FR) L'invention concerne un appareil qui comprend : un substrat ; une puce couplée au substrat ; au moins deux dispositifs actifs positionnés dans le substrat ; une pluralité de trous d'interconnexion entourant au moins l'un des deux dispositifs actifs, de telle sorte qu'une cage de Faraday est formée autour de l'au moins un des deux dispositifs actifs.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)