Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2019066859) PACKAGE ON ACTIVE SILICON SEMICONDUCTOR PACKAGES
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2019/066859 International Application No.: PCT/US2017/054038
Publication Date: 04.04.2019 International Filing Date: 28.09.2017
IPC:
H01L 25/065 (2006.01) ,H01L 25/07 (2006.01) ,H01L 23/12 (2006.01) ,H01L 23/00 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Blvd Santa Clara, California 95054, US
Inventors:
GOMES, Wilfred; US
GANESAN, Sanka; US
INGERLY, Doug; US
SANKMAN, Robert; US
BOHR, Mark; US
MALLIK, Debendra; US
Agent:
CZARNECKI, Michael S.; US
Priority Data:
Title (EN) PACKAGE ON ACTIVE SILICON SEMICONDUCTOR PACKAGES
(FR) BOÎTIER SUR BOÎTIERS DE SEMI-CONDUCTEUR AU SILICIUM ACTIF
Abstract:
(EN) Systems and methods for providing a low profile stacked die semiconductor package in which a first semiconductor package is stacked with a second semiconductor package and both semiconductor packages are conductively coupled to an active silicon substrate that communicably couples the first semiconductor package to the second semiconductor package. The first semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a first interconnect pattern having a first interconnect pitch. The second semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a second interconnect pattern having a second pitch that is greater than the first pitch. The second semiconductor package may be stacked on the first semiconductor package and conductively coupled to the active silicon substrate using a plurality of conductive members or a plurality of wirebonds.
(FR) La présente invention concerne des systèmes et des procédés destinés à fournir un boîtier de semi-conducteur de puce empilé à profil bas dans lequel un premier boîtier de semi-conducteur est empilé avec un second boîtier de semi-conducteur et les deux boîtiers de semi-conducteur sont couplés de manière conductrice à un substrat de silicium actif qui couple de manière communicative le premier boîtier de semi-conducteur au second boîtier de semi-conducteur. Le premier boîtier de semi-conducteur peut être couplé de manière conductrice au substrat de silicium actif à l'aide d'une pluralité d'interconnexions disposées selon un premier motif d'interconnexion ayant un premier pas d'interconnexion. Le second boîtier de semi-conducteur peut être couplé de manière conductrice au substrat de silicium actif à l'aide d'une pluralité d'interconnexions disposées selon un second motif d'interconnexion ayant un second pas qui est supérieur au premier pas. Le second boîtier de semi-conducteur peut être empilé sur le premier boîtier de semi-conducteur et couplé de manière conductrice au substrat de silicium actif à l'aide d'une pluralité d'éléments conducteurs ou d'une pluralité de soudures de fils.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)