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1. (WO2019066855) INTERCONNECTS HAVING A PORTION WITHOUT A LINER MATERIAL AND RELATED STRUCTURES, DEVICES, AND METHODS
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Pub. No.: WO/2019/066855 International Application No.: PCT/US2017/054018
Publication Date: 04.04.2019 International Filing Date: 28.09.2017
IPC:
H01L 21/768 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
CHANDHOK, Manish; US
SCHENKER, Richard; US
TRONIC, Tristan; US
Agent:
BOOTH, Brett C.; US
Priority Data:
Title (EN) INTERCONNECTS HAVING A PORTION WITHOUT A LINER MATERIAL AND RELATED STRUCTURES, DEVICES, AND METHODS
(FR) INTERCONNEXIONS AYANT UNE PORTION SANS MATÉRIAU DE REVÊTEMENT ET STRUCTURES, DISPOSITIFS ET PROCÉDÉS ASSOCIÉS
Abstract:
(EN) Integrated circuit (IC) structures, computing devices, and related methods are disclosed. An IC structure includes an interlayer dielectric (ILD), an interconnect, and a liner material separating the interconnect from the ILD. The interconnect includes a first end extending to or into the ILD and a second end opposite the first end. A second portion of the interconnect extending from the second end to a first portion of the interconnect proximate to the first end does not include the liner material thereon. A method of manufacturing an IC structure includes removing an ILD from between interconnects, applying a conformal hermetic liner, applying a carbon hard mask (CHM) between the interconnects, removing a portion of the CHM, removing the conformal hermetic liner to a remaining CHM, and removing the exposed portion of the liner material to the remaining CHM to expose the second portion of the interconnects.
(FR) L'invention concerne des structures de circuit intégré (CI), des dispositifs informatiques et des procédés associés. Une structure de CI comprend un diélectrique intercouche (ILD), une interconnexion et un matériau de revêtement qui sépare l'interconnexion de l'ILD. L'interconnexion comprend une première extrémité qui s'étend vers ou dans l'ILD et une deuxième extrémité opposée à la première extrémité. Le matériau de revêtement n'est pas présent sur une deuxième portion de l'interconnexion qui s'étend de la deuxième extrémité à une première portion de l'interconnexion à proximité de la première extrémité. Un procédé de fabrication d'une structure de CI comprend l'enlèvement d'un ILD d'entre des interconnexions, l'application d'un revêtement hermétique conforme, l'application d'un masque dur de carbone (CHM) entre les interconnexions, l'enlèvement d'une portion du CHM, l'enlèvement du revêtement hermétique conforme d'un CHM restant, et l'enlèvement de la portion exposée du matériau de revêtement du CHM restant pour exposer la deuxième portion des interconnexions.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)