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1. (WO2019066854) DYNAMIC RANDOM ACCESS MEMORY INCLUDING THRESHOLD SWITCH
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Pub. No.: WO/2019/066854 International Application No.: PCT/US2017/054016
Publication Date: 04.04.2019 International Filing Date: 28.09.2017
IPC:
H01L 27/108 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
108
Dynamic random access memory structures
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
SHARMA, Abhishek A.; US
PILLARISETTY, Ravi; US
DOYLE, Brian S.; US
MAJHI, Prashant; US
Agent:
PARKER, Wesley E.; US
MARLINK, Jeffrey S.; US
AUYEUNG, Al; US
RASKIN, Vladimir; US
DANSKIN, Timothy A.; US
MOORE, Michael S.; US
STRAUSS, Ryan N.; US
COFIELD, Michael A.; US
BLAIR, Steven R.; US
HALEVA, Aaron S.; US
MAKI, Nathan R.; US
WANG, Yuke; US
YATES, Steven; US
BERNADICOU, Michael A.; US
BRASK, Justin; US
Priority Data:
Title (EN) DYNAMIC RANDOM ACCESS MEMORY INCLUDING THRESHOLD SWITCH
(FR) MÉMOIRE VIVE DYNAMIQUE COMPRENANT UN COMMUTATEUR DE SEUIL
Abstract:
(EN) Described herein are apparatuses, systems, and methods associated with a memory circuit that includes memory cells having respective threshold switches. The memory cells may include a selector transistor with a gate terminal coupled to a word line to receive a word line signal, a drain terminal coupled to a bit line to receive a bit line signal, and a source terminal coupled to a first terminal of the threshold switch. The threshold switch may switch from a high resistance state to a low resistance state when a voltage across the first terminal and a second terminal exceeds a threshold voltage and may remain in the low resistance state after switching when the voltage across the first and second terminals is equal to or greater than a holding voltage that is less than the threshold voltage. Other embodiments may be described and claimed.
(FR) L'invention concerne des appareils, des systèmes et des procédés associés à un circuit de mémoire qui comprend des cellules de mémoire comportant des commutateurs de seuil respectifs. Les cellules de mémoire peuvent comprendre un transistor de sélection comportant une borne de grille couplée à un canal mot servant à recevoir un signal de canal mot, une borne de drain couplée à un canal bit servant à recevoir un signal de canal bit, et une borne de source couplée à une première borne du commutateur de seuil. Le commutateur de seuil peut passer d'un état de résistance élevée à un état de faible résistance lorsqu'une tension appliquée à la première borne et à une seconde borne dépasse une tension de seuil, et peut rester dans l'état de faible résistance après la commutation lorsque la tension appliquée aux première et seconde bornes est égale ou supérieure à une tension de maintien qui est inférieure à la tension de seuil. D'autres modes de réalisation peuvent faire l'objet d'une description et de revendications.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)