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1. (WO2019066840) QUANTUM WELL STACKS FOR QUANTUM DOT DEVICES
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Pub. No.: WO/2019/066840 International Application No.: PCT/US2017/053910
Publication Date: 04.04.2019 International Filing Date: 28.09.2017
IPC:
G06N 99/00 (2010.01) ,B82Y 10/00 (2011.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
N
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
99
Subject matter not provided for in other groups of this subclass
B PERFORMING OPERATIONS; TRANSPORTING
82
NANO-TECHNOLOGY
Y
SPECIFIC USES OR APPLICATIONS OF NANO-STRUCTURES; MEASUREMENT OR ANALYSIS OF NANO-STRUCTURES; MANUFACTURE  OR TREATMENT OF NANO-STRUCTURES
10
Nano-technology for information processing, storage or transmission, e.g. quantum computing or single electron logic
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054-1549, US
Inventors:
PILLARISETTY, Ravi; US
THOMAS, Nicole K.; US
GEORGE, Hubert C.; US
CAUDILLO, Roman; US
CLARKE, James S.; US
LE, Van H.; US
ROBERTS, Jeanette M.; US
AMIN, Payam; US
YOSCOVITS, Zachary R.; US
KOTLYAR, Roza; US
SINGH, Kanwaljit; NL
Agent:
ZAGER, Laura A.; US
Priority Data:
Title (EN) QUANTUM WELL STACKS FOR QUANTUM DOT DEVICES
(FR) STRUCTURES D'EMPILEMENT DE PUITS QUANTIQUE POUR DISPOSITIFS À POINTS QUANTIQUES
Abstract:
(EN) Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.
(FR) La présente invention concerne des dispositifs à points quantiques, ainsi que des procédés et des dispositifs informatiques associés. Par exemple, dans certains modes de réalisation, un dispositif à points quantiques peut comprendre un substrat de silicium (111), une couche de puits quantique de germanium (111) au-dessus du substrat, et une pluralité de grilles au-dessus de la couche de puits quantique. Dans certains modes de réalisation, un dispositif à points quantiques peut comprendre un substrat de silicium, un matériau isolant au-dessus du substrat de silicium, une couche de puits quantique au-dessus du matériau isolant, et une pluralité de grilles au-dessus de la couche de puits quantique.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)