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1. (WO2019066829) DIRECT SELF-ASSEMBLY PROCESS FOR FORMATION OF SELECTOR OR MEMORY LAYERS ON A VERTICAL RRAM MEMORY FOR LEAKAGE CURRENT MINIMIZATION
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Pub. No.: WO/2019/066829 International Application No.: PCT/US2017/053852
Publication Date: 04.04.2019 International Filing Date: 28.09.2017
IPC:
H01L 45/00 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
45
Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
Applicants:
LILAK, Aaron D. [US/US]; US
THEOFANIS, Patrick [US/US]; US
KENCKE, David L. [US/US]; US
KOTLYAR, Roza [US/US]; US
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
LILAK, Aaron D.; US
THEOFANIS, Patrick; US
KENCKE, David L.; US
KOTLYAR, Roza; US
Agent:
SULLIVAN, Stephen G.; US
BRASK, Justin K.; US
AUYEUNG, Al; US
BERNADICOU, Michael A.; US
BLAIR, Steven R.; US
BLANK, Eric S.; US
COFIELD, Michael A.; US
DANSKIN, Timothy A.; US
HALEVA, Aaron S.; US
MAKI, Nathan R.; US
MARLINK, Jeffrey S.; US
MOORE, Michael S.; US
PARKER, Wesley E.; US
PUGH, Joseph A.; US
RASKIN, Vladimir; US
STRAUSS, Ryan N.; US
WANG, Yuke; US
YATES, Steven D.; US
ROJO, Estiven; US
Priority Data:
Title (EN) DIRECT SELF-ASSEMBLY PROCESS FOR FORMATION OF SELECTOR OR MEMORY LAYERS ON A VERTICAL RRAM MEMORY FOR LEAKAGE CURRENT MINIMIZATION
(FR) PROCESSUS D'AUTO-ASSEMBLAGE DIRECT POUR LA FORMATION DE COUCHES DE SÉLECTION OU DE MÉMOIRE SUR UNE MÉMOIRE RRAM VERTICALE PERMETTANT DE RÉDUIRE AU MINIMUM UN COURANT DE FUITE
Abstract:
(EN) An integrated circuit structure includes a stack of alternating first conductive layers and insulator layers. A plurality of etch pits are through the first conductive layers. A plurality of selectors are in the etch pits adjacent to the first conductive layers. A memory material layer is adjacent to the plurality of selectors in the etch pits, wherein one of the plurality of selectors and the memory material layer is self-aligned and has a hemispherical side facing the corresponding etch pit.
(FR) La présente invention concerne une structure de circuit intégré qui comprend un empilement de premières couches conductrices et de couches isolantes alternées. Une pluralité de dislocations sont formées à travers les premières couches conductrices. Une pluralité de sélecteurs se trouvent dans les dislocations adjacentes aux premières couches conductrices. Une couche de matériau de mémoire est adjacente à la pluralité de sélecteurs dans les dislocations, un sélecteur de la pluralité de sélecteurs et de la couche de matériau de mémoire étant auto-aligné et comportant un côté hémisphérique faisant face à la dislocation correspondante.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)