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1. (WO2019066824) ENCAPSULATION LAYERS OF THIN FILM TRANSISTORS
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Pub. No.: WO/2019/066824 International Application No.: PCT/US2017/053842
Publication Date: 04.04.2019 International Filing Date: 27.09.2017
IPC:
H01L 29/786 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
Applicants:
SHARMA, Abhishek A. [IN/US]; US
LE, Van H. [US/US]; US
KAVALIEROS, Jack T. [US/US]; US
GHANI, Tahir [US/US]; US
DEWEY, Gilbert [US/US]; US
SHIVARAMAN, Shriram [IN/US]; US
MERIC, Inanc [TR/US]; US
CHU-KUNG, Benjamin [US/US]; US
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
SHARMA, Abhishek A.; US
LE, Van H.; US
KAVALIEROS, Jack T.; US
GHANI, Tahir; US
DEWEY, Gilbert; US
SHIVARAMAN, Shriram; US
MERIC, Inanc; US
CHU-KUNG, Benjamin; US
Agent:
WANG, Yuke; US
PUGH, Joseph A.; US
COFIELD, Michael A.; US
BLANK, Eric S.; US
ROJO, Estiven; US
BRASK, Justin K.; US
AUYEUNG, Al; US
BERNADICOU, Michael A.; US
BLAIR, Steven R.; US
DANSKIN, Timothy A.; US
HALEVA, Aaron S.; US
MAKI, Nathan R.; US
MARLINK, Jeffrey S.; US
MOORE, Michael S.; US
PARKER, Wesley E.; US
RASKIN, Vladimir; US
STRAUSS, Ryan N.; US
YATES, Steven D.; US
SULLIVAN, Stephen G.; US
Priority Data:
Title (EN) ENCAPSULATION LAYERS OF THIN FILM TRANSISTORS
(FR) COUCHES D'ENCAPSULATION DE TRANSISTORS À COUCHES MINCES
Abstract:
(EN) Embodiments herein describe techniques for a semiconductor device, which may include a substrate, a metallic encapsulation layer above the substrate, and a gate electrode above the substrate and next to the metallic encapsulation layer. A channel layer may be above the metallic encapsulation layer and the gate electrode, where the channel layer may include a source area and a drain area. In addition, a source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.
(FR) Des modes de réalisation de la présente invention décrivent des techniques pour un dispositif à semi-conducteur, qui peut comprendre un substrat, une couche d'encapsulation métallique au-dessus du substrat, et une électrode de grille au-dessus du substrat et à côté de la couche d'encapsulation métallique. Une couche de canal peut être au-dessus de la couche d'encapsulation métallique et de l'électrode de grille, la couche de canal pouvant comprendre une zone de source et une zone de drain. En outre, une électrode de source peut être couplée à la zone de source, et une électrode de drain peut être couplée à la zone de drain. D'autres modes de réalisation peuvent être décrits et/ou revendiqués.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)