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1. (WO2019066823) FERROELECTRICS USING THIN ALLOY OF PARA-ELECTRIC MATERIALS
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Pub. No.: WO/2019/066823 International Application No.: PCT/US2017/053838
Publication Date: 04.04.2019 International Filing Date: 27.09.2017
IPC:
H01L 29/78 (2006.01) ,H01L 29/51 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
43
characterised by the materials of which they are formed
49
Metal-insulator semiconductor electrodes
51
Insulating materials associated therewith
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Blvd. Santa Clara, CA 95054, US
Inventors:
AVCI, Uygar E.; US
HOWARD, Joshua M.; US
KIM, Seiyon; US
YOUNG, Ian A.; US
Agent:
MUGHAL, Usman A.; US
Priority Data:
Title (EN) FERROELECTRICS USING THIN ALLOY OF PARA-ELECTRIC MATERIALS
(FR) ÉLÉMENTS FERROÉLECTRIQUES UTILISANT UN ALLIAGE MINCE DE MATÉRIAUX PARA-ÉLECTRIQUES
Abstract:
(EN) Described is an apparatus which comprises: a first layer comprising a metal; a second layer comprising a first para-electric material, the second layer adjacent to the first layer; and a third layer comprising a second para-electric material, the third layer adjacent to the second layer, wherein the first para-electric material is different from the second para-electric material.
(FR) L'invention concerne un appareil qui comprend : une première couche comprenant un métal ; une deuxième couche comprenant un premier matériau para-électrique, la deuxième couche étant adjacente à la première couche ; et une troisième couche comprenant un second matériau para-électrique, la troisième couche étant adjacente à la deuxième couche, le premier matériau para-électrique étant différent du second matériau para-électrique.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)