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1. (WO2019066778) SOURCE/DRAIN DIFFUSION BARRIER FOR GERMANIUM NMOS TRANSISTORS
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2019/066778 International Application No.: PCT/US2017/053474
Publication Date: 04.04.2019 International Filing Date: 26.09.2017
IPC:
H01L 29/78 (2006.01) ,H01L 29/66 (2006.01) ,H01L 29/417 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
417
carrying the current to be rectified, amplified or switched
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
GLASS, Glenn A.; US
MURTHY, Anand S.; US
JAMBUNATHAN, Karthik; US
BOMBERGER, Cory C.; US
GHANI, Tahir; US
KAVALIEROS, Jack T.; US
CHU-KUNG, Benjamin; US
SUNG, Seung Hoon; US
CHOUKSEY, Siddharth; US
Agent:
ALBANEZE, Michael J.; US
Priority Data:
Title (EN) SOURCE/DRAIN DIFFUSION BARRIER FOR GERMANIUM NMOS TRANSISTORS
(FR) BARRIÈRE DE DIFFUSION SOURCE/DRAIN POUR TRANSISTORS NMOS AU GERMANIUM
Abstract:
(EN) Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the structure includes an intervening diffusion barrier deposited between the n-MOS transistor and the STI region to provide dopant diffusion reduction. In some embodiments, the diffusion barrier may include silicon dioxide with carbon concentrations between 5 and 50% by atomic percentage. In some embodiments, the diffusion barrier may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques to achieve a diffusion barrier thickness in the range of 1 to 5 nanometers.
(FR) L'invention concerne des structures de transistor pour circuit intégré qui réduisent la diffusion de dopant de type N, telle que le phosphore ou l'arsenic, depuis la région de source et la région de drain d'un dispositif N-MOS au germanium dans des régions d'isolation de tranchée peu profonde (STI) adjacentes pendant la fabrication. Le dispositif à transistor N-MOS peut comprendre au moins 75 % de germanium en pourcentage atomique. Dans un exemple de mode de réalisation, la structure comprend une barrière de diffusion intermédiaire déposée entre le transistor N-MOS et la région STI en vue de réaliser une réduction de la diffusion de dopant. Dans certains modes de réalisation, la barrière de diffusion peut comprendre du dioxyde de silicium avec des concentrations de carbone comprises entre 5 et 50 % en pourcentage atomique. Dans certains modes de réalisation, la barrière de diffusion peut être déposée en utilisant le dépôt chimique en phase vapeur (CVD), le dépôt de couche atomique (ALD) ou des techniques de dépôt physique en phase vapeur (PVD) afin d'obtenir une épaisseur de barrière de diffusion dans la plage de 1 à 5 nanomètres.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)