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1. (WO2019066775) INTEGRATED CIRCUIT STRUCTURES HAVING DIFFERENTIATED WORKFUNCTION LAYERS
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Pub. No.: WO/2019/066775 International Application No.: PCT/US2017/053430
Publication Date: 04.04.2019 International Filing Date: 26.09.2017
IPC:
H01L 27/092 (2006.01) ,H01L 21/8238 (2006.01) ,H01L 27/06 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
08
including only semiconductor components of a single kind
085
including field-effect components only
088
the components being field-effect transistors with insulated gate
092
complementary MIS field-effect transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8238
Complementary field-effect transistors, e.g. CMOS
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
06
including a plurality of individual components in a non-repetitive configuration
Applicants:
PANG, Ying [US/US]; US
GSTREIN, Florian [AT/US]; US
LAVRIC, Dan S. [RO/US]; US
AGARWAL, Ashish [IN/US]; US
NIFFENEGGER, Robert [US/US]; US
SADHUKHAN, Padmanava [IN/US]; US
HEUSSNER, Robert W. [US/US]; US
GREGIE, Joel M. [US/US]; US
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
PANG, Ying; US
GSTREIN, Florian; US
LAVRIC, Dan S.; US
AGARWAL, Ashish; US
NIFFENEGGER, Robert; US
SADHUKHAN, Padmanava; US
HEUSSNER, Robert W.; US
GREGIE, Joel M.; US
Agent:
BRASK, Justin K.; US
AUYEUNG, Al; US
BERNADICOU, Michael A.; US
BLAIR, Steven R.; US
BLANK, Eric S.; US
COFIELD, Michael A.; US
DANSKIN, Timothy A.; US
HALEVA, Aaron S.; US
MAKI, Nathan R.; US
MARLINK, Jeffrey S.; US
MOORE, Michael S.; US
PARKER, Wesley E.; US
PUGH, Joseph A.; US
RASKIN, Vladimir; US
STRAUSS, Ryan N.; US
WANG, Yuke; US
YATES, Steven D.; US
SULLIVAN, Stephen G.; US
ROJO, Estiven; US
Priority Data:
Title (EN) INTEGRATED CIRCUIT STRUCTURES HAVING DIFFERENTIATED WORKFUNCTION LAYERS
(FR) STRUCTURES DE CIRCUIT INTÉGRÉ COMPORTANT DES COUCHES À FONCTION DE TRAVAIL DIFFÉRENCIÉES
Abstract:
(EN) Integrated circuit structures having differentiated workfunction layers are described. In an example, an integrated circuit structure includes a first gate electrode above a substrate. The first gate electrode includes a first workfunction material layer. A second gate electrode is above the substrate. The second gate electrode includes a second workfunction material layer different in composition from the first workfunction material layer. The second gate electrode does not include the first workfunction material layer, and the first gate electrode does not include the second workfunction material layer. A third gate electrode above is the substrate. The third gate electrode includes a third workfunction material layer different in composition from the first workfunction material layer and the second workfunction material layer. The third gate electrode does not include the first workfunction material layer and does not include the second workfunction material layer.
(FR) L'invention concerne des structures de circuit intégré comportant des couches à fonction de travail différenciées. Selon un exemple, une structure de circuit intégré comprend une première électrode grille au-dessus d'un substrat. La première électrode grille comprend une couche de matériau à première fonction de travail. Une deuxième électrode grille se trouve au-dessus du substrat. La deuxième électrode grille comprend une couche de matériau à deuxième fonction de travail ayant une composition différente de celle de la couche de matériau à première fonction de travail. La deuxième électrode grille ne comprend pas la couche de matériau à première fonction de travail, et la première électrode grille ne comprend pas la couche de matériau à deuxième fonction de travail. Une troisième électrode grille se trouve au-dessus du substrat. La troisième électrode grille comprend une couche de matériau à troisième fonction de travail ayant une composition différente de celles de la couche de matériau à première fonction de travail et de la couche de matériau à deuxième fonction de travail. La troisième électrode grille ne comprend pas la couche de matériau à première fonction de travail ni la couche de matériau à deuxième fonction de travail.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)