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1. (WO2019066774) THIN FILM TRANSISTORS HAVING RELATIVELY INCREASED WIDTH AND SHARED BITLINES
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Pub. No.: WO/2019/066774 International Application No.: PCT/US2017/053424
Publication Date: 04.04.2019 International Filing Date: 26.09.2017
IPC:
H01L 29/786 (2006.01) ,H01L 29/49 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
43
characterised by the materials of which they are formed
49
Metal-insulator semiconductor electrodes
Applicants:
DOYLE, Brian S. [IE/US]; US
SHARMA, Abhishek A. [IN/US]; US
PILLARISETTY, Ravi [US/US]; US
MAJHI, Prashant [IN/US]; US
KARPOV, Elijah V. [US/US]; US
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
DOYLE, Brian S.; US
SHARMA, Abhishek A.; US
PILLARISETTY, Ravi; US
MAJHI, Prashant; US
KARPOV, Elijah V.; US
Agent:
SULLIVAN, Stephen G.; US
BRASK, Justin K.; US
AUYEUNG, Al; US
BERNADICOU, Michael A.; US
BLAIR, Steven R.; US
BLANK, Eric S.; US
COFIELD, Michael A.; US
DANSKIN, Timothy A.; US
HALEVA, Aaron S.; US
MAKI, Nathan R.; US
MARLINK, Jeffrey S.; US
MOORE, Michael S.; US
PARKER, Wesley E.; US
PUGH, Joseph A.; US
RASKIN, Vladimir; US
STRAUSS, Ryan N.; US
WANG, Yuke; US
YATES, Steven D.; US
ROJO, Estiven; US
Priority Data:
Title (EN) THIN FILM TRANSISTORS HAVING RELATIVELY INCREASED WIDTH AND SHARED BITLINES
(FR) TRANSISTORS À COUCHES MINCES AYANT UNE LARGEUR RELATIVEMENT ACCRUE ET DES LIGNES DE BIT PARTAGÉES
Abstract:
(EN) Thin film transistors having relatively increased width and shared bitlines are described. In an example, an integrated circuit structure includes a plurality of transistors formed in an insulator structure above a substrate. The plurality of transistors arranged in a column such that the respective lateral arrangement of the source, the gate, and the drain of each of the transistors aligns with an adjacent thin film transistor, wherein the plurality transistors extend vertically through the insulator structure at least two interconnect levels to provide increased relative width. A first conductive contact is formed between one of sources and drains of at least two of the plurality of transistors in the column, and the conductive contact extends through the insulator structure at least two interconnect levels.
(FR) L'invention concerne des transistors à couches minces ayant une largeur relativement accrue et des lignes de bit partagées. Dans un exemple, une structure de circuit intégré comprend une pluralité de transistors formés dans une structure isolante au-dessus d'un substrat. La pluralité de transistors sont disposés dans une colonne de telle sorte que la disposition latérale respective de la source, de la grille et du drain de chacun des transistors s'aligne avec un transistor à couches minces adjacent, la pluralité de transistors s'étendant verticalement à travers la structure isolante sur au moins deux niveaux d'interconnexion pour fournir une largeur relative accrue. Un premier contact conducteur est formé entre les sources ou les drains d'au moins deux transistors de la pluralité de transistors dans la colonne, et le contact conducteur s'étend à travers la structure isolante sur au moins deux niveaux d'interconnexion.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)