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1. (WO2019066766) III-N NANOSTRUCTURES FORMED VIA CAVITY FILL
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Pub. No.: WO/2019/066766 International Application No.: PCT/US2017/053348
Publication Date: 04.04.2019 International Filing Date: 26.09.2017
IPC:
H01L 29/06 (2006.01) ,H01L 21/22 (2006.01) ,H01L 21/768 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
22
Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regions; Redistribution of impurity materials, e.g. without introduction or removal of further dopant
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054-1549, US
Inventors:
RADOSAVLJEVIC, Marko; US
DASGUPTA, Sansaptak; US
THEN, Han Wui; US
Agent:
HARTMANN, Natalya; US
Priority Data:
Title (EN) III-N NANOSTRUCTURES FORMED VIA CAVITY FILL
(FR) NANOSTRUCTURES AU III-N FORMÉES PAR REMPLISSAGE DE CAVITÉ
Abstract:
(EN) A method for forming III-N structures of desired nanoscale dimensions is disclosed. The method is based on, first, providing a material to serve as a shell inside which a cavity can be formed, followed by using epitaxial growth to fill the cavity with III-N semiconductor(s). Filling a cavity of specified shape and dimensions with a III-N semiconductor results in formation of a III-N structure which has shape and dimensions defined by those of the cavity in the shell, advantageously enabling formation of III-N structures on a nanometer scale without having to rely on etching of III-N materials. Ensuring that at least a part of the III-N material in the cavity is formed by lateral epitaxial overgrowth allows obtaining high quality III-N semiconductor in that part without having to grow a thick layer. Disclosed III-N nanostructures can serve as foundation for fabricating III-N device components, e.g. III-N transistors, having non-planar architecture.
(FR) L'invention concerne un procédé de formation de structures au III-N de dimensions nanométriques souhaitées. Le procédé consiste, en premier lieu, à utiliser un matériau destiné à servir de coque à l'intérieur de laquelle peut être formée une cavité, puis à exécuter une croissance épitaxiale permettant de remplir la cavité avec un ou plusieurs semi-conducteurs au III-N. Le remplissage d'une cavité de forme et de dimensions spécifiées avec un semi-conducteur au III-N a pour conséquence la formation d'une structure au III-N qui a une forme et des dimensions définies par celles de la cavité de la coque, permettant avantageusement la formation de structures au III-N à une échelle nanométrique sans avoir recours à la gravure de matériaux de III-N. La garantie du fait qu'au moins une partie du matériau de III-N soit formée dans la cavité par une surcroissance épitaxiale latérale permet d'obtenir un semi-conducteur au III-N de haute qualité dans cette partie sans devoir faire appel à une croissance d'une couche épaisse. Les nanostructures au III-N décrites peuvent servir de base à la fabrication de composants de dispositif au III-N, par exemple de transistors au III-N, ayant une architecture non plane.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)