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1. (WO2019066264) SEMICONDUCTOR PACKAGE CLIP HAVING ENGRAVED PATTERN, LEAD FRAME, SUBSTRATE, AND SEMICONDUCTOR PACKAGE INCLUDING SAME
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2019/066264 International Application No.: PCT/KR2018/009736
Publication Date: 04.04.2019 International Filing Date: 23.08.2018
IPC:
H01L 23/31 (2006.01) ,H01L 23/13 (2006.01) ,H01L 23/495 (2006.01) ,H01L 23/00 (2006.01) ,H01L 21/48 (2006.01) ,H01L 23/40 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
28
Encapsulation, e.g. encapsulating layers, coatings
31
characterised by the arrangement
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
13
characterised by the shape
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
495
Lead-frames
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
48
Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/06-H01L21/326201
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
40
Mountings or securing means for detachable cooling or heating arrangements
Applicants:
제엠제코(주) JMJ KOREA CO., LTD. [KR/KR]; 경기도 부천시 원미구 길주로425번길 102 (도당동) (Dodang-dong) 102, Gilju-ro 425beon-gil Wonmi-gu, Bucheon-si Gyeonggi-do 14487, KR
Inventors:
최윤화 CHOI, Yun Hwa; KR
조정훈 CHO, Jeong Hun; KR
최순성 CHOI, Soon Seong; KR
Agent:
오창석 OH, Chang Suk; KR
Priority Data:
10-2017-012713429.09.2017KR
10-2017-015149214.11.2017KR
Title (EN) SEMICONDUCTOR PACKAGE CLIP HAVING ENGRAVED PATTERN, LEAD FRAME, SUBSTRATE, AND SEMICONDUCTOR PACKAGE INCLUDING SAME
(FR) AGRAFE DE BOÎTIER SEMI-CONDUCTEUR AYANT UN MOTIF GRAVÉ, GRILLE DE CONNEXION, SUBSTRAT ET BOÎTIER SEMI-CONDUCTEUR LA COMPRENANT
(KO) 음각 패턴이 형성된 반도체 패키지용 클립, 리드프레임, 기판 및 이를 포함하는 반도체 패키지
Abstract:
(EN) The present invention relates to a semiconductor package and, more particularly, to a semiconductor package clip, a lead frame, a substrate, and a semiconductor package including the same, the semiconductor package clip having engraved patterns formed on the surfaces of a metal clip, the lead frame, and the substrate, which are used in the semiconductor package, so as to increase adhesion and improve corrosion-resistant performance, thereby enabling reliability of the semiconductor package to improve.
(FR) La présente invention concerne un boîtier semi-conducteur et, plus particulièrement, une agrafe de boîtier semi-conducteur, une grille de connexion, un substrat et un boîtier semi-conducteur comprenant celle-ci, l'agrafe de boîtier semi-conducteur ayant des motifs gravés formés sur les surfaces d'une agrafe métallique, la grille de connexion et le substrat, qui sont utilisés dans le boîtier semi-conducteur, de manière à augmenter l'adhérence et à améliorer les performances de résistance à la corrosion, ce qui permet d'améliorer la fiabilité du boîtier semi-conducteur.
(KO) 본 발명은 반도체 패키지에 관한 것으로, 보다 상세하게는, 반도체 패키지에 사용되는 금속재 클립과 리드프레임, 기판의 표면에 음각 패턴이 형성되어 접착력 증대와 내부식 성능 향상으로 반도체 패키지의 신뢰성을 향상시킬 수 있는 반도체 패키지용 클립, 리드프레임, 기판 및 이를 포함하는 반도체 패키지에 관한 것이다.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Korean (KO)
Filing Language: Korean (KO)