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1. (WO2019066168) COVERING ASSEMBLY FOR PLASMA PROCESSING CHAMBER
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Pub. No.: WO/2019/066168 International Application No.: PCT/KR2018/002960
Publication Date: 04.04.2019 International Filing Date: 14.03.2018
IPC:
H01L 21/67 (2006.01) ,H01L 21/683 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
67
Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
67
Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
683
for supporting or gripping
Applicants:
비씨엔씨 주식회사 BCNC CO., LTD. [KR/KR]; 경기도 이천시 신둔면 마소로57번길 25 25, Maso-ro 57beon-gil, Sindun-myeon Icheon-si, Gyeonggi-do 17304, KR
Inventors:
김돈한 KIM, Don Han; KR
Agent:
김경환 KIM, Kyung Hwan; KR
Priority Data:
10-2017-012511927.09.2017KR
Title (EN) COVERING ASSEMBLY FOR PLASMA PROCESSING CHAMBER
(FR) ENSEMBLE DE RECOUVREMENT POUR CHAMBRE DE TRAITEMENT AU PLASMA
(KO) 플라즈마 공정 챔버의 커버링 어셈블리
Abstract:
(EN) The present invention relates to a covering assembly for encompassing an electrostatic chuck in a plasma processing chamber formed to alleviate surface damage and feature profile tilting of a semiconductor substrate. The present invention relates to a covering assembly for a plasma processing chamber, the covering assembly being formed to encompass an electrostatic chuck having an upper end surface, which supports a substrate, and a stepped annular step at the upper end surface, and comprising: a quartz ring arranged in the annular step of the electrostatic chuck so as to encompass the side surfaces of the substrate and the electrostatic chuck, and having a coupling groove formed on the lower surface thereof; and an electrode ring coupled to the coupling groove of the quartz ring so as to maintain electrical contact with the electrostatic chuck on the horizontal plane of the annular step, wherein the quartz ring has an internal transmittance of 99% or greater. According to the present invention, the surface damage and feature profile tilting of the semiconductor substrate can be alleviated.
(FR) La présente invention concerne un ensemble de recouvrement pour englober un mandrin électrostatique dans une chambre de traitement au plasma formée pour atténuer un endommagement de surface et un basculement de profil de caractéristique d'un substrat semi-conducteur. La présente invention concerne un ensemble de recouvrement pour une chambre de traitement au plasma, l'ensemble de recouvrement étant formé pour englober un mandrin électrostatique ayant une surface d'extrémité supérieure, qui supporte un substrat, et une marche annulaire étagée au niveau de la surface d'extrémité supérieure, et comprenant : un anneau de quartz agencé dans la marche annulaire du mandrin électrostatique de manière à englober les surfaces latérales du substrat et du mandrin électrostatique, et ayant une rainure de couplage formée sur sa surface inférieure ; et un anneau d'électrode couplé à la rainure de couplage de l'anneau de quartz de façon à maintenir un contact électrique avec le mandrin électrostatique sur le plan horizontal de la marche annulaire, l'anneau de quartz ayant une transmittance interne supérieure ou égale à 99 %. Selon la présente invention, les dommages de surface et le basculement de profil de caractéristique du substrat semi-conducteur peuvent être atténués.
(KO) 본 발명은 반도체 기판의 표면 손상 및 피처 프로파일 틸팅이 개선될 수 있도록 구성한 플라즈마 공정 챔버 내 정전 척을 둘러싸는 커버링 어셈블리에 관한 것이다. 본 발명은 기판을 지지하는 상단 표면과 상단 표면에서 단턱진 환형 스텝을 이루는 정전 척을 둘러싸도록 구성되는 플라즈마 공정 챔버의 커버링 어셈블리로서, 정전 척의 환형 스텝에 배치되어 기판과 정전 척의 측면을 둘러싸도록 구성되되, 하부면에는 결합홈이 형성되는 쿼츠링 및 환형 스텝의 수평면에서 정전 척과의 전기적 접촉이 유지되도록 쿼츠링의 결합홈에 결합하는 전극링을 포함하고 쿼츠링은 내부 투과율이 99% 이상인 것을 특징으로 한다. 본 발명에 의하면, 반도체 기판의 표면 손상 및 피처 프로파일 틸팅을 개선시킬 수 있는 장점이 있다.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Korean (KO)
Filing Language: Korean (KO)