Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2019065977) METHOD FOR PRODUCING MOUNTING STRUCTURE, AND SHEET USED IN SAME
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2019/065977 International Application No.: PCT/JP2018/036283
Publication Date: 04.04.2019 International Filing Date: 28.09.2018
IPC:
H01L 23/29 (2006.01) ,H01L 23/02 (2006.01) ,H01L 23/10 (2006.01) ,H01L 23/31 (2006.01) ,H01L 25/04 (2014.01) ,H01L 25/18 (2006.01) ,H03H 3/08 (2006.01) ,H03H 9/25 (2006.01) ,H05K 3/28 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
28
Encapsulation, e.g. encapsulating layers, coatings
29
characterised by the material
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
02
Containers; Seals
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
02
Containers; Seals
10
characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
28
Encapsulation, e.g. encapsulating layers, coatings
31
characterised by the arrangement
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
18
the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/-H01L51/160
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
H
IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
3
Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
007
for the manufacture of electromechanical resonators or networks
08
for the manufacture of resonators or networks using surface acoustic waves
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
H
IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
9
Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
25
Constructional features of resonators using surface acoustic waves
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
22
Secondary treatment of printed circuits
28
Applying non-metallic protective coatings
Applicants:
ナガセケムテックス株式会社 NAGASE CHEMTEX CORPORATION [JP/JP]; 大阪府大阪市西区新町1丁目1-17 1-17, Shinmachi 1-chome, Nishi-ku, Osaka-shi, Osaka 5508668, JP
Inventors:
橋本 卓幸 HASHIMOTO Takayuki; JP
石橋 卓也 ISHIBASHI Takuya; JP
岡田 浩之 OKADA Hiroyuki; JP
西村 和樹 NISHIMURA Kazuki; JP
Agent:
特許業務法人河崎・橋本特許事務所 KAWASAKI, HASHIMOTO AND PARTNERS; 大阪府大阪市中央区北浜2丁目3番6号 北浜山本ビル Kitahama-Yamamoto Building, 3-6, Kitahama 2-chome, Chuo-ku, Osaka-shi, Osaka 5410041, JP
Priority Data:
2017-19194529.09.2017JP
Title (EN) METHOD FOR PRODUCING MOUNTING STRUCTURE, AND SHEET USED IN SAME
(FR) PROCÉDÉ DE PRODUCTION DE STRUCTURE DE MONTAGE ET FEUILLE UTILISÉE DANS CELUI-CI
(JA) 実装構造体の製造方法およびこれに用いられるシート
Abstract:
(EN) This method for producing a mounting structure is provided with: a step for preparing a mounting member provided with a first circuit member, and a plurality of second circuit members mounted on the first circuit member; a step for preparing a thermosetting sheet; an arrangement step in which the sheet is arranged on the mounting member so as to face the second circuit members; and a sealing step in which the sheet is pressed against the first circuit member and heated to seal the second circuit members, and the sheet is cured. The second circuit members are provided with reference members, and first and second adjacent members which are respectively disposed adjacent to the reference members. The clearance D1 between the reference members and the first adjacent members is different to the clearance D2 between the reference members and the second adjacent members. Furthermore, at least one of the plurality of second circuit members is a hollow member provided with a space which is formed between said at least one second circuit member and the first circuit member. In the sealing step, the plurality of second circuit members are sealed while maintaining said space.
(FR) L'invention concerne un procédé de production d'une structure de montage comprenant : une étape de préparation d'un élément de montage comportant un premier élément de circuit, et une pluralité de seconds éléments de circuit montés sur le premier élément de circuit ; une étape de préparation d'une feuille thermodurcissable ; une étape d'agencement dans laquelle la feuille est disposée sur l'élément de montage de façon à faire face aux seconds éléments de circuit ; et une étape de scellement dans laquelle la feuille est pressée contre le premier élément de circuit et chauffée pour sceller les seconds éléments de circuit, et la feuille est durcie. Les seconds éléments de circuit comprennent des éléments de référence, et des premier et second éléments adjacents qui sont respectivement disposés adjacents aux éléments de référence. Le jeu D1 entre les éléments de référence et les premiers éléments adjacents est différent du jeu D2 entre les éléments de référence et les seconds éléments adjacents. En outre, au moins l'un de la pluralité de seconds éléments de circuit est un élément creux pourvu d'un espace qui est formé entre ledit au moins un second élément de circuit et le premier élément de circuit. Dans l'étape de scellement, la pluralité de seconds éléments de circuit sont scellés tout en maintenant ledit espace.
(JA) 第1回路部材と、第1回路部材に搭載される複数の第2回路部材と、を備える実装部材を準備する工程と、熱硬化性のシートを準備する工程と、シートを、第2回路部材に対向するように実装部材に配置する配置工程と、シートを第1回路部材に対して押圧するとともに、シートを加熱することにより第2回路部材を封止し、シートを硬化させる封止工程と、を具備し、第2回路部材は、基準部材と、基準部材にそれぞれ隣接する第1の隣接部材および第2の隣接部材と、を備え、基準部材と第1の隣接部材との間の離間距離D1と、基準部材と第2の隣接部材との間の離間距離D2とは、異なっており、さらに、複数の第2回路部材の少なくとも一つは、第1回路部材との間に形成される空間を備える中空部材であり、封止工程では、空間を維持しながら、複数の第2回路部材が封止される、実装構造体の製造方法。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)