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1. (WO2019065463) SEMICONDUCTOR DEVICE
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Pub. No.: WO/2019/065463 International Application No.: PCT/JP2018/034875
Publication Date: 04.04.2019 International Filing Date: 20.09.2018
IPC:
H01L 29/78 (2006.01) ,H01L 21/336 (2006.01) ,H01L 29/06 (2006.01) ,H01L 29/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
Applicants:
株式会社デンソー DENSO CORPORATION [JP/JP]; 愛知県刈谷市昭和町1丁目1番地 1-1, Showa-cho, Kariya-city, Aichi 4488661, JP
Inventors:
箕谷 周平 MITANI Shuhei; JP
池上 勝哉 IKEGAMI Katsuya; JP
副島 成雅 SOEJIMA Narumasa; JP
Agent:
特許業務法人ゆうあい特許事務所 YOU-I PATENT FIRM; 愛知県名古屋市中区錦一丁目6番5号 名古屋錦シティビル4階 Nagoya Nishiki City Bldg. 4F 1-6-5, Nishiki, Naka-ku, Nagoya-shi, Aichi 4600003, JP
Priority Data:
2017-18691627.09.2017JP
Title (EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF SEMI-CONDUCTEUR
(JA) 半導体装置
Abstract:
(EN) The present invention comprises a strongly correlated material layer (9) provided between a source electrode (11) and a gate electrode (8) of a vertical MOSFET. This makes it possible, when heat generation occurs in an element during short circuiting, to cause the strongly correlated material layer (9) to function as a conductor and cause the gate and the source of the vertical MOSFET to electrically connect. Therefore, the voltage of the gate electrode (8) can be reduced and a short-circuit current flowing in the vertical MOSFET can be cut off, making it possible to minimize the power in the vertical MOSFET.
(FR) La présente invention comprend une couche de matériau fortement liée (9) disposée entre une électrode source (11) et une électrode grille (8) d'un MOSFET vertical. Ceci permet, lorsque une production de chaleur a lieu dans un élément pendant un court-circuit, d'amener la couche de matériau fortement liée (9) à fonctionner en tant que conducteur et d'amener la grille et la source du MOSFET vertical à se raccorder électriquement. Par conséquent, la tension de l'électrode grille (8) peut être réduite et un courant de court-circuit circulant dans le MOSFET vertical peut être coupé, ce qui permet de réduire au minimum la puissance dans le MOSFET vertical.
(JA) 縦型MOSFETのゲート電極(8)とソース電極(11)との間に強相関材料層(9)を備える。これにより、短絡時に素子発熱が生じたときに、強相関材料層(9)が導体として機能し、縦型MOSFETのゲート-ソース間が導通させることができる。したがって、ゲート電極(8)の電圧を低下させることが可能となり、縦型MOSFETに流れる短絡電流を遮断できるため、縦型MOSFETでの電力を抑えることが可能となる。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)