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1. (WO2019065441) TRANSFER SUBSTRATE AND TRANSFER METHOD
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Pub. No.: WO/2019/065441 International Application No.: PCT/JP2018/034789
Publication Date: 04.04.2019 International Filing Date: 20.09.2018
IPC:
H01L 21/683 (2006.01) ,B23K 26/57 (2014.01) ,H01L 33/48 (2010.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
67
Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
683
for supporting or gripping
[IPC code unknown for B23K 26/57]
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
48
characterised by the semiconductor body packages
Applicants:
東レエンジニアリング株式会社 TORAY ENGINEERING CO., LTD. [JP/JP]; 東京都中央区八重洲1丁目3番22号(八重洲龍名館ビル) Yaesu Ryumeikan Bldg., 3-22, Yaesu 1-chome, Chuo-ku, Tokyo 1030028, JP
Inventors:
橋本 靖典 HASHIMOTO, Yasunori; JP
陣田 敏行 JINDA, Toshiyuki; JP
新井 義之 ARAI, Yoshiyuki; JP
Priority Data:
2017-19107229.09.2017JP
Title (EN) TRANSFER SUBSTRATE AND TRANSFER METHOD
(FR) SUBSTRAT DE TRANSFERT ET PROCÉDÉ DE TRANSFERT
(JA) 転写基板、及び転写方法
Abstract:
(EN) The present invention addresses the problem of alleviating impact during transfer and transferring a semiconductor chip with high accuracy. Particularly, a transfer substrate 10 for receiving the transfer of a semiconductor chip S from a transfer-source substrate and holding the semiconductor chip to transfer the semiconductor chip to the transfer-destination substrate is characterized by comprising at least: a base material 1 having a first main surface 1a and a second main surface 1b; and an impact absorbing layer 2 for absorbing the impact during the transfer of the semiconductor chip S, the impact absorbing layer being provided such that the first main surface 1a of the base material 1 is in contact with the second main surface 1b.
(FR) La présente invention aborde le problème d'atténuation d'impact lors du transfert et transférant une puce semi-conductrice avec une grande précision. En particulier, un substrat de transfert 10 pour recevoir le transfert d'une puce semi-conductrice S à partir d'un substrat de transfert source et maintenir la puce semi-conductrice pour transférer la puce semi-conductrice au substrat de transfert destination est caractérisé en ce qu'il comprend au moins : un matériau de base 1 ayant une première surface principale 1a et une seconde surface principale 1b ; et une couche d'absorption d'impact 2 pour absorber l'impact pendant le transfert de la puce semi-conductrice S, la couche d'absorption d'impact étant disposée de telle sorte que la première surface principale 1a du matériau de base 1 est en contact avec la seconde surface principale 1b.
(JA) 転写時の衝撃を緩和して高精度に半導体チップを転写することを課題とする。具体的には、転写元基板から半導体チップSを転写されるとともに、半導体チップを保持して転写先基板に転写するための転写基板10であって、第1主面1aと第2主面1bとを有した基材1と、前記基材1の第1主面1aに第2主面2bを接して設けた、半導体チップSの転写時の衝撃を緩和するための衝撃吸収層2と、を少なくとも備えたことを特徴とする転写基板の構成とした。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)