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1. (WO2019065393) IMAGING COMPONENT AND IMAGING DEVICE
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Pub. No.: WO/2019/065393 International Application No.: PCT/JP2018/034574
Publication Date: 04.04.2019 International Filing Date: 19.09.2018
IPC:
H04N 5/3745 (2011.01) ,H04N 5/347 (2011.01) ,H04N 5/369 (2011.01)
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
N
PICTORIAL COMMUNICATION, e.g. TELEVISION
5
Details of television systems
30
Transforming light or analogous information into electric information
335
using solid-state image sensors [SSIS]
369
SSIS architecture; Circuitry associated therewith
374
Addressed sensors, e.g. MOS or CMOS sensors
3745
having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
N
PICTORIAL COMMUNICATION, e.g. TELEVISION
5
Details of television systems
30
Transforming light or analogous information into electric information
335
using solid-state image sensors [SSIS]
341
Extracting pixel data from an image sensor by controlling scanning circuits, e.g. by modifying the number of pixels having been sampled or to be sampled
347
by combining or binning pixels in SSIS
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
N
PICTORIAL COMMUNICATION, e.g. TELEVISION
5
Details of television systems
30
Transforming light or analogous information into electric information
335
using solid-state image sensors [SSIS]
369
SSIS architecture; Circuitry associated therewith
Applicants:
キヤノン株式会社 CANON KABUSHIKI KAISHA [JP/JP]; 東京都大田区下丸子3丁目30番2号 30-2, Shimomaruko 3-chome, Ohta-ku, Tokyo 1468501, JP
Inventors:
内田 峰雄 UCHIDA Mineo; JP
Agent:
阿部 琢磨 ABE Takuma; JP
黒岩 創吾 KUROIWA Sogo; JP
Priority Data:
2017-19175629.09.2017JP
2017-20637925.10.2017JP
Title (EN) IMAGING COMPONENT AND IMAGING DEVICE
(FR) COMPOSANT D'IMAGERIE ET DISPOSITIF D'IMAGERIE
(JA) 撮像素子及び撮像装置
Abstract:
(EN) The present invention is characterized in that a pixel array includes multiple pixel blocks composed of multiple pixels, a signal processing unit and a corresponding pixel block are connected by multiple first signal lines, the signal processing unit and a corresponding transfer unit are connected by multiple second signal lines, the signal processing unit is provided with a conversion circuit for sequential analog-digital conversion of first signals input from the multiple first signal lines during the same period, and the transfer unit is disposed in a direction different from a first direction in which the first signal lines are disposed with respect to a circuit array on a second substrate.
(FR) La présente invention est caractérisée en ce qu'un réseau de pixels comprend de multiples blocs de pixels composés de multiples pixels, une unité de traitement de signal et un bloc de pixel correspondant sont connectés par de multiples premières lignes de signal, l'unité de traitement de signal et une unité de transfert correspondante sont connectées par de multiples secondes lignes de signal, l'unité de traitement de signal est pourvue d'un circuit de conversion pour une conversion analogique-numérique séquentielle de premiers signaux entrés à partir des multiples premières lignes de signal pendant la même période, et l'unité de transfert est disposée dans une direction différente d'une première direction dans laquelle les premières lignes de signal sont disposées par rapport à un réseau de circuits sur un second substrat.
(JA) 画素アレイは複数の画素によって形成される複数の画素ブロックを含み、信号処理部と対応する画素ブロックとは複数の第1の信号線によって接続され、信号処理部と対応する転送部とは複数の第2の信号線によって接続され、信号処理部は複数の第1の信号線から同期間に入力される第1の信号を順次アナログデジタル変換する変換回路を備え、転送部は第2の基板において回路アレイに対して第1の信号線が設けられた第1の方向とは異なる方向に配置されていることを特徴とする。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)