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1. (WO2019065208) SEMICONDUCTOR DEVICE
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Pub. No.: WO/2019/065208 International Application No.: PCT/JP2018/033568
Publication Date: 04.04.2019 International Filing Date: 11.09.2018
IPC:
H01L 21/336 (2006.01) ,H01L 21/768 (2006.01) ,H01L 23/522 (2006.01) ,H01L 29/41 (2006.01) ,H01L 29/423 (2006.01) ,H01L 29/49 (2006.01) ,H01L 29/78 (2006.01) ,H01L 29/786 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
423
not carrying the current to be rectified, amplified or switched
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
43
characterised by the materials of which they are formed
49
Metal-insulator semiconductor electrodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
Applicants:
国立研究開発法人産業技術総合研究所 NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY [JP/JP]; 東京都千代田区霞が関1丁目3番1号 3-1,Kasumigaseki 1-chome, Chiyoda-ku, Tokyo 1008921, JP
Inventors:
太田 裕之 OTA, Hiroyuki; JP
右田 真司 MIGITA, Shinji; JP
Agent:
特許業務法人筒井国際特許事務所 TSUTSUI & ASSOCIATES; 東京都新宿区新宿2丁目3番10号 新宿御苑ビル3階 3F, Shinjuku Gyoen Bldg., 3-10, Shinjuku 2-chome, Shinjuku-ku, Tokyo 1600022, JP
Priority Data:
2017-19136929.09.2017JP
Title (EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF SEMICONDUCTEUR
(JA) 半導体装置
Abstract:
(EN) According to the present invention, in order to reduce the power consumption of a semiconductor device by steepening the rise of a drain current when a field-effect transistor has a gate voltage lower than a threshold value, a fully depleted MOSFET, in which a semiconductor layer having a thickness of 20 nm or less serves as a channel region, is configured to have a gate plug which is connected to a gate electrode and which comprises a first plug, a ferroelectric film, and a second plug that are sequentially laminated on the gate electrode. In this configuration, the overlapping area size in planar view between the contact surface of the ferroelectric film to the first plug and the contact surface of the ferroelectric film to the second plug, is smaller than the overlapping area size between the gate electrode and the semiconductor layer serving as an active region.
(FR) Selon la présente invention, afin de réduire la consommation d'énergie d'un dispositif semi-conducteur par augmentation de la montée d'un courant de drain lorsqu'un transistor à effet de champ a une tension de grille inférieure à une valeur de seuil, un MOSFET complètement appauvri, dans laquelle une couche semi-conductrice ayant une épaisseur de 20 nm ou moins sert de région de canal, est configuré pour avoir une fiche de grille qui est connectée à une électrode de grille et qui comprend une première fiche, un film ferroélectrique et une seconde fiche qui sont séquentiellement stratifiées sur l'électrode de grille. Dans cette configuration, la taille de zone de chevauchement, dans une vue en plan entre la surface de contact du film ferroélectrique sur la première fiche et la surface de contact du film ferroélectrique sur la seconde fiche, est inférieure à la taille de zone de chevauchement entre l'électrode de grille et la couche semi-conductrice servant de région active.
(JA) 電界効果トランジスタのゲート電圧がしきい値電圧未満であるときのドレイン電流の立ち上がりを急峻化することで、半導体装置の消費電力を低減する。その手段として、チャネル領域である半導体層の厚さが20nm以下の完全空乏型MOSFETにおいて、ゲート電極に接続されたゲートプラグを、ゲート電極上に順に積層された第1プラグ、強誘電体膜および第2プラグにより構成する。ここで、第1プラグおよび強誘電体膜の接触面と、強誘電体膜および第2プラグの接触面とが平面視で重なる面積は、ゲート電極と活性領域である半導体層とが重なる面積よりも小さい。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)